专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06393544B1 Method and apparatus for calculating a page table index from a virtual address 有权
公开(公告)号：US06393544B1
公开(公告)日：2002-05-21
申请号：US09430793
申请日：1999-10-31
申请人： William R. Bryg , Stephen G. Burger , Gary N. Hammond , James O. Hays , Jerome C. Huck , Jonathan K. Ross , Sunil Saxena , Koichi Yamada
发明人： William R. Bryg , Stephen G. Burger , Gary N. Hammond , James O. Hays , Jerome C. Huck , Jonathan K. Ross , Sunil Saxena , Koichi Yamada
IPC分类号： G06F1200
CPC分类号： G06F12/1018 , G06F2212/652
摘要： A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single “long format” page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address. If the computer system is operating with long format page tables, the next step is to form a hash index by combining the hash page number and the region identifier referenced by the region portion of the virtual address, and to form a table offset by shifting the hash index left by K bits, wherein each long format page table entry is 2K bytes long. However, if the computer system is operating with short format page tables, the next step is to form a hash index by setting the hash index equal to the hash page number, and to form a table offset by shifting the hash index left by L bits, wherein each short format page table entry is 2L bytes long. Next, a mask is formed based on the size of the page table. A first address portion is then formed using the base address of the page table and the mask, and a second address portion is formed using the table offset and the mask. Finally, the entry address is formed by combining the first and second address portions. By providing a single algorithm capable of generating a page table entry for both long and short format page tables, the present invention reduces the amount of logic required to access both page table formats, without significantly affecting execution speed.

2. 发明授权

US06216214B1 Apparatus and method for a virtual hashed page table 失效
标题翻译：虚拟散列页表的装置和方法
公开(公告)号：US06216214B1
公开(公告)日：2001-04-10
申请号：US09018326
申请日：1998-02-03
申请人： William R. Bryg , Stephen G. Burger , James O. Hays , John M. Kessenich , Jonathan K. Ross , Gary N. Hammond , Sunil Saxena , Koichi Yamada
发明人： William R. Bryg , Stephen G. Burger , James O. Hays , John M. Kessenich , Jonathan K. Ross , Gary N. Hammond , Sunil Saxena , Koichi Yamada
IPC分类号： G06F1210
CPC分类号： G06F12/1036 , G06F2212/681
摘要： The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.
摘要翻译：本发明一般涉及利用虚拟存储器管理系统中的单个地址空间或多个地址空间模型有效地翻译虚拟地址的装置和方法。特别地，虚拟哈希页表（VHPT）是翻译后备缓冲区（TLB）层次结构的扩展，旨在增强虚拟地址转换性能。虚拟哈希页表（VHPT）有效地支持用于将虚拟地址转换为物理地址的两种操作系统的不同方法。这直接有利于地址解析高度经常的路径。

3. 发明授权

US06430670B1 Apparatus and method for a virtual hashed page table 失效
标题翻译：虚拟散列页表的装置和方法
公开(公告)号：US06430670B1
公开(公告)日：2002-08-06
申请号：US09703536
申请日：2000-11-01
申请人： William R. Bryg , Stephen G. Burger , James O. Hays , John M. Kessenich , Jonathan K. Ross , Gary N. Hammond , Sunil Saxena , Koichi Yamada
发明人： William R. Bryg , Stephen G. Burger , James O. Hays , John M. Kessenich , Jonathan K. Ross , Gary N. Hammond , Sunil Saxena , Koichi Yamada
IPC分类号： G06F1200
CPC分类号： G06F12/1036 , G06F2212/681
摘要： The present invention generally relates to an apparatus and method for efficiently translating virtual addresses utilizing either single address space or multiple address space models in a virtual memory management system. In particular, a Virtual Hash Page Table (VHPT), an extension of the Translation Lookaside Buffer (TLB) hierarchy, is designed to enhance virtual address translation performance. Virtual Hash Page Table (VHPT) efficiently supports two different methods of operating systems use to translate virtual addresses to physical addresses. This directly benefits the highly frequented path of address resolution.
摘要翻译：本发明一般涉及利用虚拟存储器管理系统中的单个地址空间或多个地址空间模型有效地翻译虚拟地址的装置和方法。特别地，虚拟哈希页表（VHPT）是翻译后备缓冲区（TLB）层次结构的扩展，旨在增强虚拟地址转换性能。虚拟哈希页表（VHPT）有效地支持用于将虚拟地址转换为物理地址的两种操作系统的不同方法。这直接有利于地址解析高度经常的路径。

4. 发明授权

US06408373B2 Method and apparatus for pre-validating regions in a virtual addressing scheme 失效
标题翻译：用于在虚拟寻址方案中预先验证区域的方法和装置
公开(公告)号：US06408373B2
公开(公告)日：2002-06-18
申请号：US09850878
申请日：2001-05-07
申请人： Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg , Rajiv Gupta , Gary N. Hammond , Koichi Yamada
发明人： Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg , Rajiv Gupta , Gary N. Hammond , Koichi Yamada
IPC分类号： G06F1200
CPC分类号： G06F12/1036
摘要： A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time. When a virtual-to-physical entry is established for a page in a region having an RID stored in a region register, the RID and VRN are stored in the appropriate fields of the TLB entry. In addition, the valid field is set and the rpV field is set to indicate that the TLB entry contains an active VRN-to-RID mapping, thereby pre-validating the region. When a physical address is translated into a virtual address, a VRN and a VPN are extracted from the virtual address and provided to the TLB. The TLB is searched to find an entry having a set valid field, a set rpV field, and VRN and VPN fields containing entries matching the VRN and VPN extracted from the virtual address. If such an entry is found, the protection and access attributes field is used to determine whether the requested access is allowed. If the requested access is allowed, the PPN from the PPN field of the TLB entry is combined with an offset from the virtual address to produce a physical address that is used to complete the memory access.
摘要翻译：一种方法和装置通过将虚拟区域号（VRN）位和区域标识符（RID）存储在翻译后备缓冲器（TLB）条目中来对虚拟寻址方案中的区域进行预验证。通过将VRN位和RID都存储在TLB表中，可以在执行大多数TLB访问时旁路区域寄存器，从而去除区域寄存器中TLB查找过程的关键路径并提高系统性能。根据本发明的TLB包括具有有效字段，区域预验证有效（rpV）字段，虚拟区域号（VRN）字段，虚拟页号（VPN）字段），区域标识符（RID）字段，保护和访问属性字段以及物理页号（PPN）字段。此外，一组区域寄存器包含在任何给定时间处于活动状态的RID。当在具有存储在区域寄存器中的RID的区域中的页面建立虚拟到物理条目时，RID和VRN被存储在TLB条目的相应字段中。另外，设置有效字段，并且设置rpV字段以指示TLB条目包含活动的VRN到RID映射，从而预先验证该区域。当物理地址被转换为虚拟地址时，从虚拟地址提取VRN和VPN，并提供给TLB。搜索TLB以找到具有设置的有效字段，集合rpV字段的条目，以及包含与从虚拟地址提取的VRN和VPN匹配的条目的VRN和VPN字段。如果找到这样的条目，则使用保护和访问属性字段来确定所请求的访问是否被允许。如果允许所请求的访问，则来自TLB条目的PPN字段的PPN与来自虚拟地址的偏移组合，以产生用于完成存储器访问的物理地址。

5. 发明授权

US5940872A Software and hardware-managed translation lookaside buffer 失效
标题翻译：软件和硬件管理的翻译后备缓冲区
公开(公告)号：US5940872A
公开(公告)日：1999-08-17
申请号：US742467
申请日：1996-11-01
申请人： Gary N. Hammond , Koichi Yamada , Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg
发明人： Gary N. Hammond , Koichi Yamada , Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg
IPC分类号： G06F12/10 , G11C12/10
CPC分类号： G06F12/1027
摘要： A translation lookaside buffer (TLB) is provided including a first storage location in the TLB for storing at least a portion of a first virtual to physical memory translation. The first storage location in the TLB is both hardware-managed and software-managed. The TLB also includes a second storage location in the TLB for storing at least a portion of a second virtual to physical memory translation. The second storage location in the TLB is only software-managed.
摘要翻译：提供了翻译后备缓冲器（TLB），包括TLB中的第一存储位置，用于存储第一虚拟到物理存储器转换的至少一部分。 TLB中的第一个存储位置是硬件管理和软件管理的。 TLB还包括TLB中的第二存储位置，用于存储第二虚拟到物理存储器转换的至少一部分。 TLB中的第二个存储位置只能由软件管理。

6. 发明授权

US06230248B1 Method and apparatus for pre-validating regions in a virtual addressing scheme 失效
标题翻译：用于在虚拟寻址方案中预先验证区域的方法和装置
公开(公告)号：US06230248B1
公开(公告)日：2001-05-08
申请号：US09170140
申请日：1998-10-12
申请人： Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg , Rajiv Gupta , Gary N. Hammon , Koichi Yamada
发明人： Stephen G. Burger , James O. Hays , Jonathan K. Ross , William R. Bryg , Rajiv Gupta , Gary N. Hammon , Koichi Yamada
IPC分类号： G06F1216
CPC分类号： G06F12/1036
摘要： A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time. When a virtual-to-physical entry is established for a page in a region having an RID stored in a region register, the RID and VRN are stored in the appropriate fields of the TLB entry. In addition, the valid field is set and the rpV field is set to indicate that the TLB entry contains an active VRN-to-RID mapping, thereby pre-validating the region. When a physical address is translated into a virtual address, a VRN and a VPN are extracted from the virtual address and provided to the TLB. The TLB is searched to find an entry having a set valid field, a set rpV field, and VRN and VPN fields containing entries matching the VRN and VPN extracted from the virtual address. If such an entry is found, the protection and access attributes field is used to determine whether the requested access is allowed. If the requested access is allowed, the PPN from the PPN field of the TLB entry is combined with an offset from the virtual address to produce a physical address that is used to complete the memory access.
摘要翻译：一种方法和装置通过将虚拟区域号（VRN）位和区域标识符（RID）存储在翻译后备缓冲器（TLB）条目中来对虚拟寻址方案中的区域进行预验证。通过将VRN位和RID都存储在TLB表中，可以在执行大多数TLB访问时旁路区域寄存器，从而去除区域寄存器中TLB查找过程的关键路径并提高系统性能。根据本发明的TLB包括具有有效字段，区域预验证有效（rpV）字段，虚拟区域号（VRN）字段，虚拟页号（VPN）字段），区域标识符（RID）字段，保护和访问属性字段以及物理页号（PPN）字段。此外，一组区域寄存器包含在任何给定时间处于活动状态的RID。当在具有存储在区域寄存器中的RID的区域中的页面建立虚拟到物理条目时，RID和VRN被存储在TLB条目的相应字段中。另外，设置有效字段，并且设置rpV字段以指示TLB条目包含活动的VRN到RID映射，从而预先验证该区域。当物理地址被转换为虚拟地址时，从虚拟地址提取VRN和VPN，并提供给TLB。搜索TLB以找到具有设置的有效字段，集合rpV字段的条目，以及包含与从虚拟地址提取的VRN和VPN匹配的条目的VRN和VPN字段。如果找到这样的条目，则使用保护和访问属性字段来确定所请求的访问是否被允许。如果允许所请求的访问，则来自TLB条目的PPN字段的PPN与来自虚拟地址的偏移组合，以产生用于完成存储器访问的物理地址。

7. 发明授权

US06088780A Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address 失效
标题翻译：使用至少一种默认页面大小和为虚拟地址空间选择的页面大小之一的页表步行器将滑动字段放置在虚拟地址中
公开(公告)号：US06088780A
公开(公告)日：2000-07-11
申请号：US829337
申请日：1997-03-31
申请人： Koichi Yamada , Gary N. Hammond , Jim Hays , Jonathan Kent Ross , Stephen Burger , William R. Bryg
发明人： Koichi Yamada , Gary N. Hammond , Jim Hays , Jonathan Kent Ross , Stephen Burger , William R. Bryg
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F2212/652
摘要： A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes each selected for translating a different set of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each of the virtual address received, the selection unit positions a field in that virtual address based on the page size selected for translating the set of virtual addresses to which that virtual address belongs. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator identifies an entry in a page table based on those bits.
摘要翻译：一种用于实现使用为虚拟地址空间选择的默认页面大小和页面大小中的至少一个来定位虚拟地址中的滑动字段的页表行进者的方法和装置。根据本发明的一个方面，提供了一种在计算机系统中使用的装置，其包括页面大小存储区域和页表行进器。页面大小存储区域用于存储每个被选择用于翻译不同虚拟地址集合的页面大小的数量。页表步行器包括耦合到页面大小存储区域的选择单元以及耦合到选择单元的页面输入地址生成器。对于接收到的每个虚拟地址，选择单元基于为了翻译该虚拟地址所属的虚拟地址集而选择的页面大小来定位该虚拟地址中的字段。响应于接收到为每个虚拟地址标识的字段中的比特，页面入口地址生成器基于这些比特识别页表中的条目。

8. 发明授权

US06209085B1 Method and apparatus for performing process switching in multiprocessor computer systems 失效
标题翻译：用于在多处理器计算机系统中执行处理切换的方法和装置
公开(公告)号：US06209085B1
公开(公告)日：2001-03-27
申请号：US08927215
申请日：1997-09-11
申请人： Gary N. Hammond , Koichi Yamada
发明人： Gary N. Hammond , Koichi Yamada
IPC分类号： G06F9312
CPC分类号： G06F9/463
摘要： A method and apparatus for reducing the amount of data copied during process switches. A method for reducing the amount of data copied during process switches is provided. In response to a processor performing a process switch to a process, a first write indication corresponding to the process is stored to indicate a first register file in the processor should not be saved. In response to the process causing the processor to write to the first register file, the first write indication is altered to indicate the first register file should be saved. In response to the processor performing a process switch from the process, a first value stored in the first register file is copied into a storage device accessible by the processor if the first write indication indicates the first register file should be saved. According to another aspect of the present invention, in response to a processor performing a process switch to a process, it is determined whether the process is likely to cause the processor to touch a first register file contained in the processor. If it was determined the process is likely to cause the processor to touch the first register file, a first value stored in a storage device accessible by the processor is loaded into the first register file. A first load indication is stored to indicate whether the first value was loaded in the preceding step. In response to the process attempting to cause the processor to touch the first register file while the first load indication indicates the first value is not loaded, the first value stored in the storage device is loaded into the first register file and the first load indication is altered to indicate the first value was loaded.
摘要翻译：一种用于减少在处理切换期间复制的数据量的方法和装置。提供了一种用于减少在处理切换期间复制的数据量的方法。响应于执行到处理的处理切换的处理器，存储对应于处理的第一写入指示，以指示处理器中的第一寄存器文件不应被保存。响应于使处理器写入第一寄存器文件的处理，第一写指示被改变以指示应该保存第一寄存器文件。响应于处理器从处理器执行处理切换，如果第一写入指示指示应该保存第一寄存器文件，则存储在第一寄存器堆中的第一值被复制到可由处理器访问的存储设备中。根据另一方面本发明的响应于处理器执行到处理的处理切换，确定处理是否可能导致处理器接触包含在处理器中的第一寄存器文件。如果确定该过程可能导致处理器触摸第一寄存器文件，则存储在由处理器访问的存储设备中的第一值被加载到第一寄存器文件中。存储第一加载指示以指示在前一步骤中是否加载了第一个值。响应于在第一加载指示指示没有加载第一值的情况下尝试使处理器触摸第一寄存器文件的过程，存储在存储设备中的第一值被加载到第一寄存器堆中，并且第一加载指示是改变以指示第一个值被加载。

9. 发明授权

US6012132A Method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table 失效
标题翻译：用于实现页表行进者的方法和装置，其使用虚拟地址中的滑动字段来识别页表中的条目
公开(公告)号：US6012132A
公开(公告)日：2000-01-04
申请号：US829782
申请日：1997-03-31
申请人： Koichi Yamada , Gary N. Hammond
发明人： Koichi Yamada , Gary N. Hammond
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F2212/652
摘要： A method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes selected for translating a number of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each virtual address received by the selection unit, the selection unit positions a field in that virtual address based on the page size selected for translating that virtual address. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator identifies an entry in a page table based on those bits.
摘要翻译：一种用于实现使用虚拟地址中的滑动字段来识别页表中的条目的页表行进器的方法和装置。根据本发明的一个方面，提供了一种在计算机系统中使用的装置，其包括页面大小存储区域和页表行进器。页面大小存储区域用于存储选择用于翻译多个虚拟地址的多个页面大小。页表步行器包括耦合到页面大小存储区域的选择单元以及耦合到选择单元的页面输入地址生成器。对于由选择单元接收的每个虚拟地址，选择单元基于为了翻译该虚拟地址而选择的页面大小来定位该虚拟地址中的字段。响应于接收到为每个虚拟地址标识的字段中的比特，页面入口地址生成器基于这些比特识别页表中的条目。

10. 发明授权

US5918251A Method and apparatus for preloading different default address translation attributes 失效
标题翻译：预加载不同默认地址转换属性的方法和装置
公开(公告)号：US5918251A
公开(公告)日：1999-06-29
申请号：US771845
申请日：1996-12-23
申请人： Koichi Yamada , Gary N. Hammond
发明人： Koichi Yamada , Gary N. Hammond
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1036 , G06F2212/654
摘要： A method and apparatus for streamlining the installation of virtual to physical address translations into a translation unit. According to one aspect of the invention, an apparatus for use in a computer system is provided that generally includes a translation unit, a default attribute storage area, and a preload unit. The translation unit stores translations for translating virtual addresses into physical addresses, and each of these translations includes an attribute field. The default translation attribute storage area stores a number of default translation attributes. The preload unit is coupled to the default translation unit and the translation unit. In response to receiving a signal from the translation unit indicating a translation for a virtual address is not stored in the translation unit, the preload unit transmits the appropriate default translation attribute to the translation unit.
摘要翻译：一种用于简化虚拟到物理地址转换到翻译单元的安装的方法和装置。根据本发明的一个方面，提供了一种在计算机系统中使用的装置，其通常包括翻译单元，默认属性存储区域和预加载单元。翻译单元存储用于将虚拟地址翻译成物理地址的翻译，并且这些翻译中的每一个包括属性字段。默认翻译属性存储区域存储多个默认翻译属性。预加载单元耦合到默认转换单元和翻译单元。响应于接收到来自翻译单元的指示虚拟地址的翻译的信号未被存储在翻译单元中，预加载单元向翻译单元发送适当的默认翻译属性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式