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1. 发明授权

US06088780A Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address 失效
标题翻译：使用至少一种默认页面大小和为虚拟地址空间选择的页面大小之一的页表步行器将滑动字段放置在虚拟地址中
公开(公告)号：US06088780A
公开(公告)日：2000-07-11
申请号：US829337
申请日：1997-03-31
申请人： Koichi Yamada , Gary N. Hammond , Jim Hays , Jonathan Kent Ross , Stephen Burger , William R. Bryg
发明人： Koichi Yamada , Gary N. Hammond , Jim Hays , Jonathan Kent Ross , Stephen Burger , William R. Bryg
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F2212/652
摘要： A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes each selected for translating a different set of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each of the virtual address received, the selection unit positions a field in that virtual address based on the page size selected for translating the set of virtual addresses to which that virtual address belongs. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator identifies an entry in a page table based on those bits.
摘要翻译：一种用于实现使用为虚拟地址空间选择的默认页面大小和页面大小中的至少一个来定位虚拟地址中的滑动字段的页表行进者的方法和装置。根据本发明的一个方面，提供了一种在计算机系统中使用的装置，其包括页面大小存储区域和页表行进器。页面大小存储区域用于存储每个被选择用于翻译不同虚拟地址集合的页面大小的数量。页表步行器包括耦合到页面大小存储区域的选择单元以及耦合到选择单元的页面输入地址生成器。对于接收到的每个虚拟地址，选择单元基于为了翻译该虚拟地址所属的虚拟地址集而选择的页面大小来定位该虚拟地址中的字段。响应于接收到为每个虚拟地址标识的字段中的比特，页面入口地址生成器基于这些比特识别页表中的条目。

2. 发明授权

US6006325A Method and apparatus for instruction and data serialization in a computer processor 失效
标题翻译：计算机处理器中指令和数据串行化的方法和装置
公开(公告)号：US6006325A
公开(公告)日：1999-12-21
申请号：US769784
申请日：1996-12-19
申请人： Stephen Burger , Gary N. Hammond , William R. Bryg
发明人： Stephen Burger , Gary N. Hammond , William R. Bryg
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3802 , G06F9/30087 , G06F9/3834
摘要： A new instruction that ensures that the effects of a control register write will be observed at a well defined time is introduced. Specifically, the present invention introduces the concept of a serialization fence instruction. The serialization fence instruction ensures that after a control register in a computer has been modified, all subsequent instructions will observe the effects of the control register modification. Two different serialization fence instructions are illustrated: a data memory reference serialization fence instruction (SRLZ.d) and an instruction fetch serialization fence instruction (SRLZ.i). The data memory reference serialization fence instruction ensures that subsequent instruction executions and data memory references will observe the effects of the control register write. The instruction fetch serialization fence instruction ensures that the entire machine pipeline, starting at the initial instruction fetch stage, will observe the effects of the control register write.
摘要翻译：介绍了一个新的指令，确保控制寄存器写入的效果将在明确的时间内被观察到。具体地，本发明引入了序列化栅栏指令的概念。序列化栅栏指令确保在计算机中的控制寄存器已被修改后，所有后续指令将观察到控制寄存器修改的影响。说明了两个不同的序列化栅栏指令：数据存储器引用序列化栅栏指令（SRLZ.d）和指令获取序列化栅栏指令（SRLZ.i）。数据存储器引用序列化栅栏指令确保后续指令执行和数据存储器引用将观察到控制寄存器写入的影响。指令获取序列化栅栏指令确保从初始指令读取阶段开始的整个机器流水线将观察到控制寄存器写入的影响。

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