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1. 发明授权

US5317715A Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics 失效
标题翻译：减少的指令集计算机系统包括用于将高性能RISC接口耦合到具有不同性能特性的外围总线的装置和方法
公开(公告)号：US5317715A
公开(公告)日：1994-05-31
申请号：US911783
申请日：1992-07-10
申请人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
发明人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
IPC分类号： G06F13/28 , G06F13/40 , G06F13/00 , G06F13/23
CPC分类号： G06F13/4013 , G06F13/28
摘要： Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.
摘要翻译：公开了用于向简化指令集计算机（RISC）系统的本地总线传输数据的方法和装置，包括至少一个中央处理器（“CPU”）的第一组高性能设备，和远程总线，第二组相对较低性能的设备以不限制RISC处理器性能的方式连接到该远程总线。根据本发明的优选实施例，公开了一种RISC架构，其包括新颖的数据传输控制器（“DTC”）或一组DTC，适用于在高性能本地总线与一个或多个本地总线之间执行上述数据传输功能通常具有不同（和较低）性能特征的完整子系统或外设的远程总线。由此产生的RISC节点允许商业化的外围设备和子系统与高性能RISC处理器配合使用，而不会限制RISC系统的性能。

2. 发明授权

US5142672A Data transfer controller incorporating direct memory access channels and address mapped input/output windows 失效
标题翻译：数据传输控制器包含直接存储器访问通道和地址映射输入/输出窗口
公开(公告)号：US5142672A
公开(公告)日：1992-08-25
申请号：US132296
申请日：1987-12-15
申请人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
发明人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the above transfer function in a manner that facilitates communication between the first and second set of devices from the compartively lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ("DTC") is disclosed that includes a set of direct memory access ("DMA") channels and an input/output controller comprising a set of address mapped I/O ports. Both the DMA channels and I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DTC interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance.

3. 发明授权

US4878166A Direct memory access apparatus and methods for transferring data between buses having different performance characteristics 失效
标题翻译：用于在具有不同性能特征的总线之间传送数据的直接存储器存取装置和方法
公开(公告)号：US4878166A
公开(公告)日：1989-10-31
申请号：US133094
申请日：1987-12-15
申请人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
发明人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the transfer function in a manner that facilitates communication between the first and second set of devices from the comparatively lower performance of the second set of devices. Direct memory access ("DMA") apparatus and methods are disclosed, including a set of direct memory access channels. The DMA channels may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DMA interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance. The noval DMA may also be used as part of a data transfer controller (DTC) having other components, such as I/O ports, or may be used independently for transferring data between unmatched buses in, for example, computer systems, data transmission systems and the like.

4. 发明授权

US6054881A Input/output (I/O) buffer selectively providing resistive termination for a transmission line coupled thereto 失效
标题翻译：输入/输出（I / O）缓冲器选择性地为耦合到其的传输线提供电阻终端
公开(公告)号：US6054881A
公开(公告)日：2000-04-25
申请号：US5234
申请日：1998-01-09
申请人： David W. Stoenner
发明人： David W. Stoenner
IPC分类号： H03B1/00
CPC分类号： H04L25/0292 , H04L25/0298
摘要： An input/output (I/O) buffer is presented which selectively provides resistive termination for a transmission line coupled to an input/output node. The I/O buffer includes the input/output node, a first output driver stage, a second output driver stage, a differential amplifier, and an input termination stage. The first output driver stage is enabled when resistive termination of the transmission line is not required (e.g., when an older bus standard is to be supported). The second output driver stage is enabled when resistive termination of the transmission line is required (e.g., when a higher performance bus is to be supported). The differential amplifier produces a logic high input signal when a voltage driven upon the input/output node by the transmission line is greater than a reference voltage, and produces a logic low input signal at the output terminal when the voltage driven upon the input/output node by the transmission line is less than the reference voltage. In one embodiment, the input termination stage includes a termination node, a resistive element coupled between the input/output node and the termination node, and a time delay unit. The time delay unit receives the input signal produced by the differential amplifier and produces a time-delayed input signal after a predetermined time delay has elapsed. The termination node is selectively coupled to either the power supply potential or the ground potential dependent upon the time-delayed input signal produced by the time delay unit.
摘要翻译：提出了一种输入/输出（I / O）缓冲器，其选择性地为耦合到输入/输出节点的传输线提供电阻性终端。 I / O缓冲器包括输入/输出节点，第一输出驱动级，第二输出驱动级，差分放大器和输入终端级。当不需要传输线的电阻终止时（例如，当要支持旧的总线标准时），第一个输出驱动级被使能。当需要传输线的电阻终止时（例如，当要支持更高性能总线时），第二个输出驱动级被使能。当通过传输线驱动输入/输出节点的电压大于参考电压时，差分放大器产生逻辑高输入信号，并且当输入/输出驱动的电压在输出端产生逻辑低输入信号节点由传输线小于参考电压。在一个实施例中，输入终端级包括终端节点，耦合在输入/输出节点与终端节点之间的电阻元件以及时间延迟单元。时间延迟单元接收由差分放大器产生的输入信号，并且在经过预定的时间延迟之后产生时间延迟的输入信号。终端节点选择性地耦合到电源电位或接地电位，这取决于由延时单元产生的时间延迟的输入信号。

5. 发明授权

US5134699A Programmable burst data transfer apparatus and technique 失效
标题翻译：可编程数据传输设备和技术
公开(公告)号：US5134699A
公开(公告)日：1992-07-28
申请号：US211357
申请日：1988-06-24
申请人： Percy R. Aria , David W. Stoenner
发明人： Percy R. Aria , David W. Stoenner
IPC分类号： G06F12/02 , G06F12/08 , G06F13/28 , G11C7/00
CPC分类号： G06F13/28 , G06F12/0215 , G06F12/0879
摘要： A data processing system having a processor capable of initiating a request for a burst of data transfer and a memory. A memory controller is connected to the processor and to the memory. The controller includes a burst count register having a value stored therein representative of the maximum number of data transfers allowed per burst. Also in the memory controller is a column latch/counter having stored therein a value representative of a column latch address. The column latch/counter is capable of incrementing the address. Finally, included in the memory controller is a programmable mask for specifying bits in the column latch/counter to be compared to corresponding bits in the burst count register.

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