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1. 发明申请

US20070228458A1 DUAL METAL INTEGRATION SCHEME BASED ON FULL SILICIDATION OF THE GATE ELECTRODE 失效
标题翻译：基于门电极全硅酸化的双金属一体化方案
公开(公告)号：US20070228458A1
公开(公告)日：2007-10-04
申请号：US11308486
申请日：2006-03-29
申请人： William Henson , Kern Rim , Jack Mandelman
发明人： William Henson , Kern Rim , Jack Mandelman
IPC分类号： H01L21/8234
CPC分类号： H01L21/823443 , H01L21/82345 , H01L21/823835 , H01L21/823842
摘要： An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration scheme creates different silicon thicknesses of the gate electrode just prior to silicidation. This feature of the present invention allows for fabricating nFETs and pFETs that have a band edge workfunction that is tailored for the specific device region.
摘要翻译：提供了与源极/漏极区域同时实现nFET和pFET栅电极的全硅化（FUSI）的集成方案。栅电极的FUSI消除了多晶硅栅电极观察到的栅耗尽问题。此外，本发明的集成方案刚好在硅化之前产生栅电极的不同硅厚度。本发明的该特征允许制造具有针对特定器件区域定制的带边缘功能函数的nFET和pFET。

2. 发明申请

US20070069300A1 PLANAR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR CHANNEL MOSFET WITH EMBEDDED SOURCE/DRAIN 审中-公开
标题翻译：具有嵌入式源/漏极的平面超薄半导体绝缘体通道MOSFET
公开(公告)号：US20070069300A1
公开(公告)日：2007-03-29
申请号：US11162959
申请日：2005-09-29
申请人： Kangguo Cheng , Dureseti Chidambarrao , Brian Greene , Jack Mandelman , Kern Rim
发明人： Kangguo Cheng , Dureseti Chidambarrao , Brian Greene , Jack Mandelman , Kern Rim
IPC分类号： H01L29/94
CPC分类号： H01L21/2652 , H01L21/02203 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。超薄（UT）绝缘体上半导体通道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。第一BOX区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的第二BOX区域的上部自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二个深度。

3. 发明申请

US20080064162A1 VERTICAL SOI TRANSISTOR MEMORY CELL AND METHOD OF FORMING THE SAME 失效
标题翻译：垂直SOI晶体管存储单元及其形成方法
公开(公告)号：US20080064162A1
公开(公告)日：2008-03-13
申请号：US11931238
申请日：2007-10-31
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/10841 , H01L27/10864
摘要： The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node dielectric layer located between the outer electrode and the inner electrode. The vertical transistor is located over the trench capacitor and comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The channel region of the vertical transistor is located in a tensilely or compressively strained semiconductor layer that is oriented perpendicularly to a surface of the semiconductor substrate. Preferably, the tensilely or compressively strained semiconductor layer is embedded in an insulator structure, so that the vertical transistor has a semiconductor-on-insulator (SOI) configuration.
摘要翻译：本发明涉及包含至少一个沟槽电容器和至少一个垂直晶体管的半导体器件，以及用于形成这种半导体器件的方法。具体地，沟槽电容器位于半导体衬底中，并且包括外电极，内电极和位于外电极和内电极之间的节点电介质层。垂直晶体管位于沟槽电容器上方，并包括源极区，漏极区，沟道区，栅极电介质和栅电极。垂直晶体管的沟道区域位于垂直于半导体衬底的表面定向的拉伸或压缩应变的半导体层中。优选地，拉伸或压缩应变的半导体层嵌入绝缘体结构中，使得垂直晶体管具有绝缘体上半导体（SOI）构造。

4. 发明申请

US20080052659A1 Electrically Programmable pi-Shaped Fuse Structures and Design Process Therefore 失效
标题翻译：电可编程的pi形保险丝结构和设计过程
公开(公告)号：US20080052659A1
公开(公告)日：2008-02-28
申请号：US11923833
申请日：2007-10-25
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： G06F17/50
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void. The design structure for the fuse is embodied in a machine-readable medium for designing, manufacturing or testing a design of the fuse.
摘要翻译：提出了用于集成电路的电可编程保险丝及其设计结构，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙之上。保险丝的设计结构体现在用于设计，制造或测试保险丝设计的机器可读介质中。

5. 发明申请

US20080042219A1 finFET Device 审中-公开
标题翻译： finFET器件
公开(公告)号：US20080042219A1
公开(公告)日：2008-02-21
申请号：US11923121
申请日：2007-10-24
申请人： Roger Booth , William Hovis , Jack Mandelman
发明人： Roger Booth , William Hovis , Jack Mandelman
IPC分类号： H01L29/94
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET, a method of fabricating the finFET and a design structure of the finFET. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The finFET includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET，finFET的制造方法以及finFET的设计结构。该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 finFET包括在finFET的硅体和衬底之间的体接触。

6. 发明申请

US20080042204A1 METHODS FOR FABRICATING A SEMICONDUCTOR STRUCTURE USING A MANDREL AND SEMICONDUCTOR STRUCTURES FORMED THEREBY 审中-公开
公开(公告)号：US20080042204A1
公开(公告)日：2008-02-21
申请号：US11924875
申请日：2007-10-26
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L29/66795
摘要： Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon of the body. The mandrel may be composed of porous silicon and the body may be fabricated using either a semiconductor-on-insulator substrate or a bulk substrate. The body may be used to fabricate a fin body of a fin-type field effect transistor.

7. 发明申请

US20070247273A1 ELECTRICALLY PROGRAMMABLE PI-SHAPED FUSE STRUCTURES AND METHODS OF FABRICATION THEREOF 失效
公开(公告)号：US20070247273A1
公开(公告)日：2007-10-25
申请号：US11768254
申请日：2007-06-26
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： H01H85/06 , H01L21/336 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.

8. 发明申请

US20070235833A1 Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures 失效
标题翻译：具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法
公开(公告)号：US20070235833A1
公开(公告)日：2007-10-11
申请号：US11393142
申请日：2006-03-30
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman
IPC分类号： H01L29/00
CPC分类号： H01L27/10841 , H01L27/10864
摘要： Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.
摘要翻译：具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法。半导体结构包括限定在与沟槽的侧壁相邻的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。半导体材料的中间区域分离第一和第二掺杂区域。第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。用于形成掺杂区域的方法包括沉积掺杂有掺杂剂或不同层的材料的层，每个掺杂剂或不同的层在沟槽中掺杂有一种掺杂剂，然后将掺杂剂从层或层扩散到与沟槽接壤的半导体材料侧壁。

9. 发明申请

US20070210890A1 Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
标题翻译：具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上
公开(公告)号：US20070210890A1
公开(公告)日：2007-09-13
申请号：US11372387
申请日：2006-03-09
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01H85/04
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

10. 发明申请

US20070210363A1 Vertical SOI transistor memory cell and method of forming the same 失效
标题翻译：垂直SOI晶体管存储单元及其形成方法
公开(公告)号：US20070210363A1
公开(公告)日：2007-09-13
申请号：US11308105
申请日：2006-03-07
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/10841 , H01L27/10864
摘要： The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node dielectric layer located between the outer electrode and the inner electrode. The vertical transistor is located over the trench capacitor and comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The channel region of the vertical transistor is located in a tensilely or compressively strained semiconductor layer that is oriented perpendicularly to a surface of the semiconductor substrate. Preferably, the tensilely or compressively strained semiconductor layer is embedded in an insulator structure, so that the vertical transistor has a semiconductor-on-insulator (SOI) configuration.
摘要翻译：本发明涉及包含至少一个沟槽电容器和至少一个垂直晶体管的半导体器件，以及用于形成这种半导体器件的方法。具体地，沟槽电容器位于半导体衬底中，并且包括外电极，内电极和位于外电极和内电极之间的节点电介质层。垂直晶体管位于沟槽电容器上方，并包括源极区，漏极区，沟道区，栅极电介质和栅电极。垂直晶体管的沟道区域位于垂直于半导体衬底的表面定向的拉伸或压缩应变的半导体层中。优选地，拉伸或压缩应变的半导体层嵌入绝缘体结构中，使得垂直晶体管具有绝缘体上半导体（SOI）构造。

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