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1. 发明授权

US07200719B2 Prefetch control in a data processing system 有权
标题翻译：数据处理系统中的预取控制
公开(公告)号：US07200719B2
公开(公告)日：2007-04-03
申请号：US10631136
申请日：2004-09-09
申请人： William C. Moyer , Lea Hwang Lee , Afzal M. Malik
发明人： William C. Moyer , Lea Hwang Lee , Afzal M. Malik
IPC分类号： G06F12/00 , G06F9/34
CPC分类号： G06F12/0215 , Y02D10/13
摘要： In one embodiment, a data processing system (10) includes a first master, storage circuitry (35) coupled to the first master (12) for use by the first master (12), a first control storage circuit (38) which stores a first prefetch limit (60), a prefetch buffer (42), and prefetch circuitry (40) coupled to the first control storage circuit, to the prefetch buffer, and to the storage circuitry. In one embodiment, the prefetch circuitry (40) selectively prefetches a predetermined number of lines from the storage circuitry into the prefetch buffer (42) based on whether or not a prefetch counter, initially set to a value indicated by the first prefetch limit, has expired. In one embodiment, the first prefetch limit may therefore be used to control how many prefetches occur between misses in the prefetch buffer.
摘要翻译：在一个实施例中，数据处理系统（10）包括第一主机，耦合到第一主机（12）以供第一主机（12）使用的存储电路（35），第一控制存储电路（38）第一预取限制（60），预取缓冲器（42）和耦合到第一控制存储电路的预取电路（40）到预取缓冲器以及存储电路。在一个实施例中，预取电路（40）基于是否初始设置为由第一预取限制指示的值的预取计数器是否具有预取数计数器（40）具有预定数量的行从存储电路到预取缓冲器（42）已过期在一个实施例中，因此可以使用第一预取限制来控制在预取缓冲器中的未命中之间发生多少个预取。

2. 发明授权

US06775765B1 Data processing system having instruction folding and method thereof 有权
标题翻译：具有指令折叠的数据处理系统及其方法
公开(公告)号：US06775765B1
公开(公告)日：2004-08-10
申请号：US09498814
申请日：2000-02-07
申请人： Lea Hwang Lee , William C. Moyer
发明人： Lea Hwang Lee , William C. Moyer
IPC分类号： G06F938
CPC分类号： G06F9/325 , G06F9/30058 , G06F9/3017 , G06F9/324 , G06F9/3455 , G06F9/383 , G06F9/3832 , G06F9/3838 , G06F9/3842
摘要： Embodiments of the present invention relate generally to data processing systems having instruction folding and methods for controlling execution of a program loop. One embodiment includes detecting execution of a program loop and prefetching data in response to detecting execution of the program loop. Another embodiment includes detecting execution of a program loop and scanning the program loop for remote independent instructions or data dependencies during at least one iteration. Another embodiment includes detecting execution of a program loop and storing intra-loop data dependency information in a dependency bit vector, and using the dependency bit vector to select at least one local independent instruction available for folding. One embodiment includes an instruction folding unit comprising a first controller, a second controller, and a storage unit coupled to the second controller. Another embodiment includes a data processing system comprising a validation counter and a storage unit coupled to the validation counter where the storage unit includes a dependency bit vector corresponding to instructions of a program loop.
摘要翻译：本发明的实施例一般涉及具有指令折叠的数据处理系统和用于控制程序循环执行的方法。一个实施例包括响应于检测到程序循环的执行来检测程序循环的执行和预取数据。另一个实施例包括在至少一次迭代期间检测程序循环的执行和扫描用于远程独立指令或数据依赖性的程序循环。另一个实施例包括检测程序循环的执行并将循环中的数据依赖性信息存储在依赖性位向量中，并且使用相关性位向量来选择可用于折叠的至少一个本地独立指令。一个实施例包括指令折叠单元，包括第一控制器，第二控制器和耦合到第二控制器的存储单元。另一个实施例包括数据处理系统，其包括验证计数器和耦合到验证计数器的存储单元，其中存储单元包括与程序循环的指令相对应的依赖性位向量。

3. 发明授权

US06401196B1 Data processor system having branch control and method thereof 失效
标题翻译：具有分支控制的数据处理器系统及其方法
公开(公告)号：US06401196B1
公开(公告)日：2002-06-04
申请号：US09100669
申请日：1998-06-19
申请人： Lea Hwang Lee , William C. Moyer , Jeffrey W. Scott , John H. Arends
发明人： Lea Hwang Lee , William C. Moyer , Jeffrey W. Scott , John H. Arends
IPC分类号： G06F912
CPC分类号： G06F9/324 , G06F9/325
摘要： A specific implementation is disclosed where a backward branch address instruction is fetched at a branch address. The backward branch instruction has an offset value to define the size of a program loop. A counter is set to a value that is proportional to the size of the loop. In one example the counter is set to the offset value. As each instruction of the loop is executed the counter is modified to indicate a remaining number of instructions in the loop. When no instructions remain in the current pass of the loop, the counter is reset to the offset value and the loop is repeated until a termination condition encountered. As part of the implementation the instruction after the branch instruction is read and stored prior to the loop being executed.
摘要翻译：公开了在分支地址处取出反向分支地址指令的具体实现。后向分支指令具有一个偏移值，用于定义程序循环的大小。计数器设置为与循环大小成比例的值。在一个示例中，计数器设置为偏移值。当执行循环的每个指令时，计数器被修改以指示循环中剩余的指令数。当循环当前通过中没有指令时，计数器将重置为偏移值，并重复循环直到遇到终止条件。作为实现的一部分，在循环执行之前读取并存储分支指令之后的指令。

4. 发明申请

US20080040591A1 METHOD FOR DETERMINING BRANCH TARGET BUFFER (BTB) ALLOCATION FOR BRANCH INSTRUCTIONS 审中-公开
标题翻译：用于确定分支指令分配目标缓冲区（BTB）分配的方法
公开(公告)号：US20080040591A1
公开(公告)日：2008-02-14
申请号：US11464112
申请日：2006-08-11
申请人： William C. Moyer , Lea Hwang Lee
发明人： William C. Moyer , Lea Hwang Lee
IPC分类号： G06F15/00
CPC分类号： G06F9/30058 , G06F9/30145 , G06F9/30167 , G06F9/3806 , G06F9/3846 , G06F11/0721 , G06F11/076
摘要： A method of profiling each of a plurality of branch instructions to determine when allocation of an entry in a branch target buffer should occur if the branch is taken. Various factors are used in the determination. In one form, each of the plurality of branch instructions is analyzed to determine a count value of how many times a branch instruction, when executed, is taken during a timeframe. Based upon said analyzing, an instruction field within each of the plurality of branch instructions is set to a value that controls whether allocation of an entry of a branch target buffer should occur when such branch instruction is taken. Other factors, such as determining how long each branch instruction will likely remain in the branch target buffer prior to being replaced, may be used.
摘要翻译：分析多个分支指令中的每一个以确定分支目标缓冲器中的条目的分配何时应该发生的方法。在测定中使用了各种因素。在一种形式中，分析多个分支指令中的每一个以确定在执行期间在一段时间帧期间多少次分支指令的计数值。基于所述分析，将多个分支指令中的每一个内的指令字段设置为控制当执行分支指令时是否应当发生分支目标缓冲器的条目的分配的值。可以使用其他因素，例如确定在被替换之前每个分支指令可能保留在分支目标缓冲器中的时间长度。

5. 发明授权

US5920890A Distributed tag cache memory system and method for storing data in the same 失效
标题翻译：分布式标签缓存存储器系统和存储数据的方法
公开(公告)号：US5920890A
公开(公告)日：1999-07-06
申请号：US748856
申请日：1996-11-14
申请人： William C. Moyer , Lea Hwang Lee , John Arends
发明人： William C. Moyer , Lea Hwang Lee , John Arends
IPC分类号： G06F9/32 , G06F9/38 , G06F12/08 , G06F12/12
CPC分类号： G06F9/381 , G06F12/0875
摘要： A loop cache (26) is used in a data processing system for supplying instructions to a CPU to avoid accessing a main memory. Whether instructions stored in the loop cache can be supplied to the CPU is determined by a distributed TAG associated with the instruction address computed by the CPU. The instruction address includes an LCACHE index portion (42), an ITAG portion (44), and a GTAG (46). LCACHE index (42) selects corresponding locations in each of an ITAG array (50), an instruction array (52), and a valid bit array (54). A stored GTAG value (48) is chosen irrespective of where LCACHE index (42) is pointing. The GTAG portion of the instruction address (40) is compared to the stored GTAG value (48). The ITAG portion (44) of instruction address (40) is compared with the indexed ITAG of the ITAG array (50). If both the GTAG and ITAG compare favorably, the instruction is supplied from the loop cache to the CPU, rather than from main memory.
摘要翻译：在数据处理系统中使用循环高速缓存（26），用于向CPU提供指令以避免访问主存储器。存储在循环高速缓存中的指令是否可以提供给CPU由与CPU计算的指令地址相关联的分布式TAG来确定。指令地址包括LCACHE索引部分（42），ITAG部分（44）和GTAG（46）。 LCACHE索引（42）选择ITAG阵列（50），指令阵列（52）和有效位阵列（54）中的每一个中的对应位置。选择存储的GTAG值（48），而与LCACHE索引（42）指向的位置无关。将指令地址（40）的GTAG部分与存储的GTAG值（48）进行比较。指令地址（40）的ITAG部分（44）与ITAG阵列（50）的索引ITAG进行比较。如果GTAG和ITAG都比较好，则该指令从循环高速缓存提供给CPU，而不是从主内存提供。

6. 发明授权

US07447886B2 System for expanded instruction encoding and method thereof 有权
标题翻译：扩展指令编码系统及其方法
公开(公告)号：US07447886B2
公开(公告)日：2008-11-04
申请号：US10127087
申请日：2002-04-22
申请人： Lea Hwang Lee , William C. Moyer
发明人： Lea Hwang Lee , William C. Moyer
IPC分类号： G06F9/44 , G06F9/302
CPC分类号： G06F9/30181
摘要： A system and methods are discussed for providing additional capabilities to some instructions associated with loop execution. A standard set of instructions is processed using only a standard instruction size. Some loop instructions are processed with a standard instruction portion of the standard instruction size and an augmented instruction portion. The augmented instruction portion provides additional capabilities associated with the standard instruction portion. The augmented instruction portion can provide capabilities associated with conditional execution of the standard instruction portion or other instructions within a program loop. Furthermore, the augmented instruction portion can provide an additional operand to be used with the standard instruction portion.
摘要翻译：讨论了一种系统和方法，用于为与循环执行相关的一些指令提供附加功能。仅使用标准指令大小来处理标准的指令集。一些循环指令用标准指令大小的标准指令部分和扩充指令部分进行处理。增强指令部分提供与标准指令部分相关联的附加功能。增强指令部分可以提供与程序循环内的标准指令部分或其他指令的条件执行相关联的能力。此外，扩充指令部分可以提供要与标准指令部分一起使用的附加操作数。

7. 发明申请

US20080040590A1 SELECTIVE BRANCH TARGET BUFFER (BTB) ALLOCAITON 审中-公开
标题翻译：选择性分支目标缓冲区（BTB）ALLOCAITON
公开(公告)号：US20080040590A1
公开(公告)日：2008-02-14
申请号：US11464108
申请日：2006-08-11
申请人： Lea Hwang Lee , William C. Moyer
发明人： Lea Hwang Lee , William C. Moyer
IPC分类号： G06F15/00
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/30145
摘要： Information is processed in a data processing system having a branch target buffer (BTB). In one form, an instruction is received and decoded. A determination is made whether the instruction is a taken branch instruction based on a condition code value set by one of a logical operation, an arithmetic operation or a comparison result of the execution of another instruction or execution of the instruction. An instruction specifier associated with the taken branch instruction is used to determine whether to allocate an entry of the branch target buffer for storing a branch target of the taken branch instruction. In one form the instruction specifier is a field of the instruction. Depending upon the value of the branch target buffer allocation specifier, the instruction fetch unit will not allocate an entry in the branch target buffer for unconditional branch instructions.
摘要翻译：在具有分支目标缓冲器（BTB）的数据处理系统中处理信息。在一种形式中，接收并解码指令。基于由逻辑运算，算术运算或执行另一指令的比较结果或指令的执行中的一个设置的条件代码值，确定指令是否是采取的转移指令。与采取的分支指令相关联的指令说明符用于确定是否分配用于存储所采取的分支指令的分支目标的分支目标缓冲器的条目。在一种形式中，指令说明符是指令的一个字段。根据分支目标缓冲区分配指定符的值，指令提取单元将不会在分支目标缓冲区中分配用于无条件分支指令的条目。

8. 发明授权

US06795908B1 Method and apparatus for instruction execution in a data processing system 有权
标题翻译：用于在数据处理系统中执行指令的方法和装置
公开(公告)号：US06795908B1
公开(公告)日：2004-09-21
申请号：US09591938
申请日：2000-06-12
申请人： Lea Hwang Lee , William C. Moyer
发明人： Lea Hwang Lee , William C. Moyer
IPC分类号： G06F15177
CPC分类号： G06F9/30043 , G06F9/30145 , G06F9/30189 , G06F9/322 , G06F9/345 , G06F9/3455 , G06F9/3824 , G06F9/3885
摘要： A method for processing scalar and vector executions, where vector executions may be “true” vector operations, CVA, or pseudo-vector operations, PVA. All three types of executions are processed using one architecture. In one embodiment, a compiler analyzes code to identify sections that are vectorizable, and applies either CVA, PVA, or a combination of the two to process these sections. Register overlay is provided for storing load address information and data in PVA mode. Within each CVA and PVA instruction, enable bits describe the data streaming function of the operation. A temporary memory, TM, accommodates variable size vectors, and is used in vector operations, similar to a vector register, to store temporary vectors.
摘要翻译：一种用于处理标量和矢量执行的方法，其中矢量执行可能是“真实”矢量操作，CVA或伪矢量操作，PVA。所有三种类型的执行都使用一种架构进行处理。在一个实施例中，编译器分析代码以识别可向量化的部分，并且应用CVA，PVA或两者的组合来处理这些部分。提供寄存器覆盖用于在PVA模式下存储负载地址信息和数据。在每个CVA和PVA指令中，使能位描述操作的数据流功能。临时存储器TM容纳可变大小向量，并且用于矢量操作，类似于向量寄存器，以存储临时向量。

9. 发明授权

US5893142A Data processing system having a cache and method therefor 失效
标题翻译：数据处理系统具有缓存及其方法
公开(公告)号：US5893142A
公开(公告)日：1999-04-06
申请号：US748855
申请日：1996-11-14
申请人： William C. Moyer , John Arends , Lea Hwang Lee
发明人： William C. Moyer , John Arends , Lea Hwang Lee
IPC分类号： G06F9/38 , G06F12/08 , G06F12/12 , G06F13/00
CPC分类号： G06F9/381 , G06F12/0875 , G06F2212/1028 , Y02B60/1225
摘要： A data processing system (20) has a cache (26) that does not use a TAG array for storing a TAG address as in a conventional cache. The cache (26), according to one embodiment, uses a state machine (30) for transitioning the cache (26) to an active state in response to a change of flow instruction which is a short backward branch instruction of a predetermined displacement. The predetermined displacement is less than the number of entries in the cache (26), so the cache can remain active as long as the program is in a loop which can be contained entirely within the cache. A look ahead feature for the valid bit array is provided that associates the valid bit for a current instruction with a previous instruction, such that during a read of the cache, the valid bit for a next instruction is checked with the same index used to read the current instruction.
摘要翻译：数据处理系统（20）具有如常规高速缓存中那样不使用用于存储TAG地址的TAG阵列的高速缓存（26）。根据一个实施例，根据一个实施例，高速缓存（26）使用状态机（30）来响应于作为预定位移的短反向分支指令的流指令的改变而将高速缓存（26）转换到活动状态。预定位移小于高速缓存（26）中的条目数量，因此只要程序处于可以完全包含在高速缓存内的循环，高速缓存就可以保持活动状态。提供了有效位阵列的前瞻特征，其将当前指令的有效位与先前指令相关联，使得在高速缓存的读取期间，使用用于读取的相同索引检查下一个指令的有效位当前指令。

10. 发明授权

US09389859B2 Device and method for implementing address buffer management of processor 有权
标题翻译：用于实现处理器地址缓冲区管理的设备和方法
公开(公告)号：US09389859B2
公开(公告)日：2016-07-12
申请号：US14005719
申请日：2011-08-24
申请人： Lea Hwang Lee , Chunyu Tian , Hui Ren
发明人： Lea Hwang Lee , Chunyu Tian , Hui Ren
IPC分类号： G06F9/30 , G06F9/345
CPC分类号： G06F9/30043 , G06F9/30 , G06F9/3455
摘要： The disclosure provides a device for implementing address buffer management of a processor, including: an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values; and a processor configured to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation, so as to achieve the address buffer management. The disclosure also provides a method for implementing address buffer management of a processor, including: a processor decodes a set instruction for an address automatic-increment value and boundary values to obtain intermediate values, and determines, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to realize the address buffer management. Through the device and the method of the disclosure, the hardware costs of the processor are reduced and design requirements of the processor's time sequence and energy efficiency are met.
摘要翻译：本发明提供了一种用于实现处理器的地址缓冲器管理的设备，包括：汇编器，被配置为当汇编器对地址自动增量值和边界值的设置指令进行编码时，执行操作以获得中间值，并且封装中间值进入地址自动递增值和边界值的设置指令; 以及处理器，被配置为根据中间值确定是否执行地址自动递增操作或地址自动递减操作，以便实现地址缓冲器管理。本公开还提供了一种用于实现处理器的地址缓冲器管理的方法，包括：处理器对地址自动增量值和边界值的设置指令进行解码以获得中间值，并根据中间值确定是否执行地址自动递增运算或地址自动递减运算，以便实现地址缓存管理。通过本发明的装置和方法，降低了处理器的硬件成本，满足了处理器的时序和能量效率的设计要求。

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