专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5119483A Application of state silos for recovery from memory management exceptions 失效
标题翻译：从内存管理异常中应用状态孤岛进行恢复
公开(公告)号：US5119483A
公开(公告)日：1992-06-02
申请号：US221944
申请日：1988-07-20
申请人： William C. Madden , Douglas E. Sanders , G. Michael Uhler , William R. Wheeler
发明人： William C. Madden , Douglas E. Sanders , G. Michael Uhler , William R. Wheeler
IPC分类号： G06F9/26 , G06F9/30 , G06F9/38 , G06F12/10
CPC分类号： G06F9/3867 , G06F9/26 , G06F9/30149 , G06F9/3863 , G06F12/10 , Y10S707/99939
摘要： To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with "state silos" that are operative during normal instruction execution to save a sufficient amount of state information to immediately restart the instruction decoder segment and the first execution segment by reloading the state information having been stored in the state silos. The state silos, for example, include a queue of registers clocked by a common clocking signal that is inhibited during correction of the fault. When the fault is corrected, multiplexers select the state information from the silos to be used by the respective pipeline segments. In a preferred embodiment, the instruction decoder segment decodes variable length macroinstructions into operand specifiers and operations to perform upon the specifiers. The first execution segment receives control information when a new operand specifier or operation is decoded, and otherwise holds the previously received control information. A microsequencer issues a series of microinstructions for each specifier or operation having been decoded, and also issues a series of microinstructions in a fault routine when a fault occurs. The microsequencer is also provided with a state silo so that the normal sequence of microinstruction execution is resumed when the fault is corrected.
摘要翻译：为了减少纠正故障所需的处理时间，流水线处理器的指令解码段和第一执行段被提供有在正常指令执行期间操作的“状态仓”以保存足够量的状态信息以立即重启指令解码器段和第一执行段，通过重新加载已经存储在状态列表中的状态信息。例如，状态孤岛包括由校正故障期间被禁止的公共时钟信号计时的寄存器队列。当故障被纠正时，多路复用器从相应流水线段使用的筒仓中选择状态信息。在优选实施例中，指令解码器段将可变长度宏指令解码为操作数说明符和在指定符上执行的操作。当新的操作数说明符或操作被解码时，第一执行段接收控制信息，否则保持先前接收到的控制信息。微定序器为每个说明符或操作已经解码了一系列微指令，并且在出现故障时也会在故障程序中发出一系列微指令。微定序器还设置有状态仓，使得当故障被校正时，微指令执行的正常序列被恢复。

2. 发明授权

US06240508B1 Decode and execution synchronized pipeline processing using decode generated memory read queue with stop entry to allow execution generated memory read 失效
标题翻译：解码和执行同步流水线处理使用解码生成的内存读取队列与停止条目允许执行生成的内存读取
公开(公告)号：US06240508B1
公开(公告)日：2001-05-29
申请号：US08505810
申请日：1995-07-21
申请人： John F. Brown, III , G. Michael Uhler , William R. Wheeler
发明人： John F. Brown, III , G. Michael Uhler , William R. Wheeler
IPC分类号： G06F938
CPC分类号： G06F9/3867 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A macropipelined microprocessor chip adheres to strict read and write ordering by sequentially buffering operands in queues during instruction decode, then removing the operands in order during instruction execution. Any instruction that requires additional access to memory inserts the requests into the queued sequence (in a specifier queue) such that read and write ordering is preserved. A specifier queue synchronization counter captures synchronization points to coordinate memory request operations among the autonomous instruction decode unit, instruction execution unit, and memory sub-system. The synchronization method does not restrict the benefit of overlapped execution in the pipelined. Another feature is treatment of a variable bit field operand type that does not restrict the location of operand data. Instruction execution flows in a pipelined processor having such an operand type are vastly different depending on whether operand data resides in registers or memory. Thus, an operand context queue (field queue) is used to simplify context-dependent execution flow and increase overlap. The field queue allows the instruction decode unit to issue instructions with variable bit field operands normally, sequentially identifying and fetching operands, and communicating the operand context that specifies register or memory residence across the pipeline boundaries to the autonomous execution unit. The mechanism creates opportunity for increasing the overlap of pipelined functions and greatly simplifies the splitting of execution flows.
摘要翻译：宏指令微处理器芯片通过在指令解码期间依次缓冲队列中的操作数，然后在指令执行期间依次移除操作数，从而遵循严格的读写顺序。任何需要对内存进行访问的指令将请求插入排队的序列（在指定符队列中），以便保留读写顺序。指定符队列同步计数器捕获同步点以协调自主指令解码单元，指令执行单元和存储器子系统之间的存储器请求操作。同步方法不限制流水线重叠执行的好处。另一个特征是处理不限制操作数数据位置的可变位字段操作数类型。具有这种操作数类型的流水线处理器中的指令执行流程根据操作数数据位于寄存器或存储器中而大不相同。因此，操作数上下文队列（字段队列）用于简化上下文相关的执行流程并增加重叠。字段队列允许指令解码单元通常发送具有可变位字段操作数的指令，顺序地识别和取出操作数，以及将指定流水线边界的寄存器或存储器驻留的操作数上下文传送到自主执行单元。该机制为增加流水线功能的重叠创造了机会，并大大简化了执行流程的拆分。

3. 发明申请

US20090024804A1 MEMORY CONTROLLERS FOR PROCESSOR HAVING MULTIPLE PROGRAMMABLE UNITS 有权
标题翻译：具有多个可编程单元的处理器的存储器控制器
公开(公告)号：US20090024804A1
公开(公告)日：2009-01-22
申请号：US12207476
申请日：2008-09-09
申请人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
发明人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
IPC分类号： G06F12/10
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。

4. 发明授权

US07107201B2 Simulating a logic design 有权
标题翻译：模拟逻辑设计
公开(公告)号：US07107201B2
公开(公告)日：2006-09-12
申请号：US09941952
申请日：2001-08-29
申请人： William R. Wheeler , Matthew J. Adiletta
发明人： William R. Wheeler , Matthew J. Adiletta
IPC分类号： G06F17/50 , G06F9/455 , G06F9/44
CPC分类号： G06F17/5022
摘要： Simulating a logic design having combinatorial logic and state logic includes representing the combinatorial logic and the state logic using separate graphic elements, identifying clock domains for the combinatorial logic and the state logic using the separate graphic elements, generating computer code that simulates operation of portions of the logic design, the computer code being generated based on the clock domains, and associating the computer code with graphic elements that correspond to the portions of the logic design.
摘要翻译：模拟具有组合逻辑和状态逻辑的逻辑设计包括使用分离的图形元素表示组合逻辑和状态逻辑，识别用于组合逻辑的时钟域和使用分离的图形元素的状态逻辑，生成计算机代码，其模拟部分的操作逻辑设计，基于时钟域产生的计算机代码，以及将计算机代码与对应于逻辑设计的部分的图形元素相关联。

5. 发明授权

US07093224B2 Model-based logic design 有权
公开(公告)号：US07093224B2
公开(公告)日：2006-08-15
申请号：US09941158
申请日：2001-08-28
申请人： William R. Wheeler , Matthew J. Adiletta , Christopher Clark , Timothy J. Fennel
发明人： William R. Wheeler , Matthew J. Adiletta , Christopher Clark , Timothy J. Fennel
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.

6. 发明授权

US07073156B2 Gate estimation process and method 失效
标题翻译：门估计过程和方法
公开(公告)号：US07073156B2
公开(公告)日：2006-07-04
申请号：US09941519
申请日：2001-08-29
申请人： William R. Wheeler , Matthew J. Adiletta
发明人： William R. Wheeler , Matthew J. Adiletta
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5045
摘要： A circuit design parameter file is maintained for a circuit being designed by a circuit designer. This circuit design parameter file specifies a physical characteristic of the circuit. A design environment is monitored to detect the addition of a circuitry component to the circuit and a component design parameter file that specifies at least one design parameter for that added circuitry component is accessed. The circuit design parameter file is updated based on the design parameter(s) included in the component design parameter file. The circuit designer is provided with feedback concerning the physical characteristic of the circuit being designed.
摘要翻译：为由电路设计者设计的电路维护电路设计参数文件。该电路设计参数文件指定电路的物理特性。监视设计环境以检测电路组件到电路的添加，并且访问指定所添加的电路组件的至少一个设计参数的组件设计参数文件。电路设计参数文件根据组件设计参数文件中包含的设计参数进行更新。电路设计人员提供有关正在设计的电路的物理特性的反馈。

7. 发明授权

US06983350B1 SDRAM controller for parallel processor architecture 失效
标题翻译：用于并行处理器架构的SDRAM控制器
公开(公告)号：US06983350B1
公开(公告)日：2006-01-03
申请号：US09387109
申请日：1999-08-31
申请人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
发明人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。

8. 发明授权

US06721925B2 Employing intelligent logical models to enable concise logic representations for clarity of design description and for rapid design capture 失效
标题翻译：采用智能逻辑模型来实现简洁的逻辑表示，以便设计描述清晰，并能快速设计
公开(公告)号：US06721925B2
公开(公告)日：2004-04-13
申请号：US10025193
申请日：2001-12-18
申请人： William R. Wheeler , Timothy J. Fennell , Matthew J. Adiletta
发明人： William R. Wheeler , Timothy J. Fennell , Matthew J. Adiletta
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5045
摘要： Representing a logic device generally includes creating a model of a logic device, where the model represents a collection of variants of the logic device. A representation of the model may be used in a logic design and a particular variant of the logic device may be selected automatically based on connections made to the representation. Connection errors may be detected automatically and a first indication may be displayed automatically when the connection errors are detected. A second indication that differs from the first indication may be displayed automatically when the connection errors are corrected.
摘要翻译：代表逻辑设备通常包括创建逻辑设备的模型，其中模型表示逻辑设备的变体的集合。可以在逻辑设计中使用该模型的表示，并且可以基于对表示形成的连接来自动选择逻辑设备的特定变体。可以自动检测连接错误，并且当检测到连接错误时可以自动显示第一指示。当修正连接错误时，可以自动显示与第一指示不同的第二指示。

9. 发明授权

US4302721A Non-contacting resistivity instrument with structurally related conductance and distance measuring transducers 失效
标题翻译：具有结构相关电导和距离测量传感器的非接触电阻率仪器
公开(公告)号：US4302721A
公开(公告)日：1981-11-24
申请号：US39303
申请日：1979-05-15
申请人： Karel Urbanek , George J. Kren , William R. Wheeler
发明人： Karel Urbanek , George J. Kren , William R. Wheeler
IPC分类号： G01N27/02 , G01R31/26 , G01R31/265 , G01R31/28 , G01S15/32 , G01N27/72 , G01R33/12
CPC分类号： G01N27/023 , G01R31/2648 , G01R31/265 , G01R31/2831 , G01S15/32 , Y10S414/135
摘要： An instrument for computing resistivity based upon measurements of thickness and conductance. A conductance transducer is a solenoid in an annular ferrite cup connected to a tank circuit for an eddy current measurement of conductance. Within the center of the annular ferrite cup concentric acoustic wave sending and receiving channels are disposed for making an acoustic pressure wave measurement which is used for a thickness measurement using two gauge heads, spaced on opposite sides of an article to be measured. Each gauge head contains identical conductance and thickness transducers. The thickness measurement is divided by the conductance measurement to derive resistivity.
摘要翻译：基于厚度和电导测量计算电阻率的仪器。电导传感器是连接到用于电导涡流测量的电路的环形铁氧体杯中的螺线管。在环形铁氧体杯的中心内，设置同心声波发送和接收通道，用于进行声压测量，其用于使用两个测量头进行厚度测量，间隔在待测物品的相对两侧。每个测量头包含相同的电导和厚度换能器。厚度测量除以电导测量以导出电阻率。

10. 发明授权

US10032431B2 Mobile computing device technology and systems and methods utilizing the same 有权
公开(公告)号：US10032431B2
公开(公告)日：2018-07-24
申请号：US14768141
申请日：2014-03-13
申请人： Myles Wilde , Matthew J. Adiletta , William R. Wheeler , Michael F. Fallon , Thomas M. Garrison , Aaron Gorius , Chengda Yang
发明人： Myles Wilde , Matthew J. Adiletta , William R. Wheeler , Michael F. Fallon , Thomas M. Garrison , Aaron Gorius , Chengda Yang
IPC分类号： G09G5/00 , H04L29/06 , G06F13/38 , H04N19/423 , H04N19/44 , G06T1/60 , H04N5/38 , H04W4/18 , H04W4/21 , H04W4/80 , H04W76/14
摘要： Mobile computing device technology and systems and methods using the same are described herein. In particular, mobile computing devices that may serve as a processing component of a disaggregated computing system described, non-integral screens that may be paired with the mobile computing devices, and systems and methods using such devices and screens are described. In some embodiments, the mobile computing device technology includes a mobile computing device that lacks an integral screen, but which is capable of throwing at least video information to a non-integral target screen, e.g., via a paired connection established over a wired or wireless communication interface.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式