专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5960293A Methods including oxide masks for fabricating capacitor structures for integrated circuit devices 失效
标题翻译：包括用于制造用于集成电路器件的电容器结构的氧化物掩模的方法
公开(公告)号：US5960293A
公开(公告)日：1999-09-28
申请号：US806080
申请日：1997-02-25
申请人： Weon-cheol Hong , Yun-seung Shin
发明人： Weon-cheol Hong , Yun-seung Shin
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for forming a capacitor for an integrated circuit device includes the following steps. An interlayer dielectric layer is formed on a substrate, and a contact hole is formed in the interlayer dielectric layer. A first conductive layer is then formed on the interlayer dielectric layer, wherein the first conductive layer is electrically connected to the substrate through the contact hole. A hole having a depth less than the thickness of the first conductive layer is etched in the first conductive layer. An insulating layer is formed in the hole and the first conductive layer is then etched to a predetermined depth using the insulating layer as an etching mask to expose a side wall of an upper portion of the insulating layer. A spacer is formed on the side wall of the upper portion of the insulating layer. The first conductive layer is then etched using the insulating layer and the spacer as etching marks to form an electrode structure. The insulating layer and spacer are then removed. Lastly, the capacitor is completed by forming a dielectric layer on the electrode structure and then forming a second conductive layer on the dielectric layer.
摘要翻译：一种用于形成用于集成电路器件的电容器的方法包括以下步骤。在基板上形成层间电介质层，在层间电介质层中形成接触孔。然后在层间电介质层上形成第一导电层，其中第一导电层通过接触孔与基板电连接。在第一导电层中蚀刻深度小于第一导电层的厚度的孔。在孔中形成绝缘层，然后使用绝缘层作为蚀刻掩模将第一导电层蚀刻到预定深度，以暴露绝缘层的上部的侧壁。在绝缘层的上部的侧壁上形成间隔物。然后使用绝缘层和间隔物作为蚀刻标记来蚀刻第一导电层以形成电极结构。然后去除绝缘层和间隔物。最后，通过在电极结构上形成电介质层，然后在电介质层上形成第二导电层来完成电容器。

2. 发明授权

US06465895B1 Bonding pad structures for semiconductor devices and fabrication methods thereof 失效
标题翻译：用于半导体器件的接合焊盘结构及其制造方法
公开(公告)号：US06465895B1
公开(公告)日：2002-10-15
申请号：US09826590
申请日：2001-04-05
申请人： Young-hoon Park , Eun-young Min , Weon-cheol Hong
发明人： Young-hoon Park , Eun-young Min , Weon-cheol Hong
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/05666 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01022 , H01L2924/014 , H01L2924/14 , H01L2224/45099
摘要： The present invention is directed to a semiconductor structure, and a fabrication technique for forming such a structure, configured to confine and prevent expansion of cracking of the insulating layer below a bonding pad, that are generated as a result of the bonding process. In a first embodiment, the present invention includes a vertical frame, formed, for example of conductive material, surrounding the outer perimeter of the bonding pad, and extending through an underlying insulating layer. A horizontal frame lies below the vertical frame. Together, the vertical frame and horizontal frame confine cracks emanating below the bonding pad to within the frame region. In a second embodiment, horizontal and vertical portions of the frame are formed by a conductive layer provided in an opening formed in the insulating layer. Since the isolation frame prevents cracks from expanding into surrounding regions of the integrated circuit, overall process yield and reliability are improved.
摘要翻译：本发明涉及一种用于形成这种结构的半导体结构和制造技术，其被配置为限制并防止由于接合工艺而产生的绝缘层在焊盘下方的开裂的膨胀。在第一实施例中，本发明包括垂直框架，其例如由导电材料形成，围绕焊盘的外周边并延伸穿过下面的绝缘层。水平框架位于垂直框架下方。垂直框架和水平框架一起将焊接垫下方的裂纹限制在框架区域内。在第二实施例中，框架的水平和垂直部分由设置在绝缘层中形成的开口中的导电层形成。由于隔离框架防止裂纹扩展到集成电路的周围区域，因此整体工艺产量和可靠性得到改善。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式