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1. 发明申请

US20080146012A1 NOVEL METHOD TO ADJUST WORK FUNCTION BY PLASMA ASSISTED METAL INCORPORATED DIELECTRIC 审中-公开
标题翻译：通过等离子体辅助金属合成电介质调整工作功能的新方法
公开(公告)号：US20080146012A1
公开(公告)日：2008-06-19
申请号：US11695227
申请日：2007-04-02
申请人： Wenli Lin , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee , Mong-Song Liang
发明人： Wenli Lin , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee , Mong-Song Liang
IPC分类号： H01L21/3205 , H01L21/31
CPC分类号： H01L21/3115 , H01L21/28185 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric on a substrate; introducing metal dopants into the gate dielectric; annealing the gate dielectric; and forming a gate electrode on the gate dielectric.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成栅极电介质; 将金属掺杂剂引入栅极电介质中; 退火栅电介质; 以及在栅极电介质上形成栅电极。

2. 发明授权

US07812414B2 Hybrid process for forming metal gates 有权
标题翻译：用于形成金属门的混合工艺
公开(公告)号：US07812414B2
公开(公告)日：2010-10-12
申请号：US11656711
申请日：2007-01-23
申请人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
发明人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

3. 发明授权

US08836038B2 CMOS dual metal gate semiconductor device 有权
标题翻译： CMOS双金属栅极半导体器件
公开(公告)号：US08836038B2
公开(公告)日：2014-09-16
申请号：US12883241
申请日：2010-09-16
申请人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
发明人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/28 , H01L29/66
CPC分类号： H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

4. 发明授权

US08536660B2 Hybrid process for forming metal gates of MOS devices 有权
标题翻译：用于形成MOS器件的金属栅极的混合工艺
公开(公告)号：US08536660B2
公开(公告)日：2013-09-17
申请号：US12047113
申请日：2008-03-12
申请人： Peng-Fu Hsu , Yong-Tian Hou , Ssu-Yi Li , Kuo-Tai Huang , Mong Song Liang
发明人： Peng-Fu Hsu , Yong-Tian Hou , Ssu-Yi Li , Kuo-Tai Huang , Mong Song Liang
IPC分类号： H01L21/02
CPC分类号： H01L21/823857 , H01L21/823842 , H01L27/092
摘要： A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.
摘要翻译：半导体结构包括包括第一栅极的第一MOS器件和包括第二栅极的第二MOS器件。第一栅极包括在半导体衬底上的第一高k电介质; 第一高k电介质上的第二高k电介质; 在所述第二高k电介质上的第一金属层，其中所述第一金属层支配所述第一MOS器件的功函数; 以及在所述第一金属层上的第二金属层。第二栅极包括半导体衬底上的第三高k电介质，其中第一和第三高k电介质由相同的材料形成，并具有基本上相同的厚度; 在所述第三高k电介质上的第三金属层，其中所述第三金属层和所述第二金属层由相同的材料形成，并且具有基本相同的厚度; 以及在第三金属层上的第四金属层。

5. 发明申请

US20090230479A1 Hybrid Process for Forming Metal Gates of MOS Devices 有权
标题翻译： MOS器件金属门的混合工艺
公开(公告)号：US20090230479A1
公开(公告)日：2009-09-17
申请号：US12047113
申请日：2008-03-12
申请人： Peng-Fu Hsu , Yong-Tian Hou , Ssu-Yi Li , Kuo-Tai Huang , Mong Song Liang
发明人： Peng-Fu Hsu , Yong-Tian Hou , Ssu-Yi Li , Kuo-Tai Huang , Mong Song Liang
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823842 , H01L27/092
摘要： A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.
摘要翻译：半导体结构包括包括第一栅极的第一MOS器件和包括第二栅极的第二MOS器件。第一栅极包括在半导体衬底上的第一高k电介质; 第一高k电介质上的第二高k电介质; 在所述第二高k电介质上的第一金属层，其中所述第一金属层支配所述第一MOS器件的功函数; 以及在所述第一金属层上的第二金属层。第二栅极包括半导体衬底上的第三高k电介质，其中第一和第三高k电介质由相同的材料形成，并具有基本上相同的厚度; 在所述第三高k电介质上的第三金属层，其中所述第三金属层和所述第二金属层由相同的材料形成，并且具有基本相同的厚度; 以及在第三金属层上的第四金属层。

6. 发明申请

US20080173947A1 Hybrid process for forming metal gates 有权
标题翻译：用于形成金属门的混合工艺
公开(公告)号：US20080173947A1
公开(公告)日：2008-07-24
申请号：US11656711
申请日：2007-01-23
申请人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , K. T. Huang , Tze-Liang Lee
发明人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , K. T. Huang , Tze-Liang Lee
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

7. 发明申请

US20110001194A1 Hybrid Process for Forming Metal Gates 有权
标题翻译：用于形成金属门的混合工艺
公开(公告)号：US20110001194A1
公开(公告)日：2011-01-06
申请号：US12883241
申请日：2010-09-16
申请人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , K. T. Huang , Tze-Liang Lee
发明人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , K. T. Huang , Tze-Liang Lee
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

8. 发明申请

US20100044804A1 NOVEL HIGH-K METAL GATE STRUCTURE AND METHOD OF MAKING 审中-公开
标题翻译：新型高K金属结构及其制备方法
公开(公告)号：US20100044804A1
公开(公告)日：2010-02-25
申请号：US12427222
申请日：2009-04-21
申请人： Chien-Hao Chen , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang
发明人： Chien-Hao Chen , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/28088 , H01L21/28194 , H01L21/28247 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length.
摘要翻译：本公开提供了一种半导体器件，其包括半导体衬底，形成在衬底中的晶体管，晶体管包括形成在衬底上的高k栅极电介质，高k栅极电介质具有从一个侧壁到高k栅极电介质的另一个侧壁和形成在高k栅极电介质上的金属栅极，金属栅极具有从金属栅极的一个侧壁到另一侧壁测量的第二长度，第二长度小于第一长。

9. 发明授权

US08324090B2 Method to improve dielectric quality in high-k metal gate technology 有权
标题翻译：提高高k金属栅极技术介质质量的方法
公开(公告)号：US08324090B2
公开(公告)日：2012-12-04
申请号：US12338787
申请日：2008-12-18
申请人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Yong-Tian Hou , Carlos H. Diaz
发明人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Yong-Tian Hou , Carlos H. Diaz
IPC分类号： H01L21/4763 , H01L25/11 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L29/513 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和金属层。

10. 发明授权

US07989321B2 Semiconductor device gate structure including a gettering layer 有权
标题翻译：包括吸气层的半导体器件栅极结构
公开(公告)号：US07989321B2
公开(公告)日：2011-08-02
申请号：US12257165
申请日：2008-10-23
申请人： Chien-Hao Chen , Yong-Tian Hou , Peng-Fu Hsu , Kuo-Tai Huang , Donald Y. Chao , Cheng-Lung Hung
发明人： Chien-Hao Chen , Yong-Tian Hou , Peng-Fu Hsu , Kuo-Tai Huang , Donald Y. Chao , Cheng-Lung Hung
IPC分类号： H01L21/322 , H01L21/32
CPC分类号： H01L21/28518 , H01L21/28185 , H01L21/3221 , H01L29/49 , H01L29/51 , H01L29/513
摘要： A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.
摘要翻译：提供了一种方法，其允许通过减小栅极结构中的界面层的厚度来维持期望的等效氧化物厚度（EOT）。在基板上形成界面层，在界面层上形成栅极电介质层，例如高k栅极电介质。在覆盖界面层的基板上形成吸气层。吸气层可用于从界面层吸收氧气，使得界面层厚度减少和/或限制生长。

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