专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08656088B2 Optimized flash based cache memory 失效
标题翻译：优化基于闪存的高速缓存
公开(公告)号：US08656088B2
公开(公告)日：2014-02-18
申请号：US13112894
申请日：2011-05-20
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotem , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotem , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.
摘要翻译：本发明的实施例涉及对闪存设备的限制访问。闪存设备是包括闪存设备和第二存储设备的存储系统的一部分。节流由闪存设备外部的逻辑执行，并且包括响应于闪存设备的估计剩余寿命来计算节流因子。确定节流因子是否超过阈值。响应于确定节流因子不超过阈值，将数据写入闪存设备。响应于确定节流因子超过阈值，将数据写入第二存储器件。

2. 发明申请

US20120297127A1 OPTIMIZED FLASH BASED CACHE MEMORY 失效
公开(公告)号：US20120297127A1
公开(公告)日：2012-11-22
申请号：US13553194
申请日：2012-07-19
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/02
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

3. 发明申请

US20120297113A1 OPTIMIZED FLASH BASED CACHE MEMORY 失效
标题翻译：优化的基于闪存的高速缓存存储器
公开(公告)号：US20120297113A1
公开(公告)日：2012-11-22
申请号：US13112894
申请日：2011-05-20
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/02
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.
摘要翻译：本发明的实施例涉及对闪存设备的限制访问。闪存设备是包括闪存设备和第二存储设备的存储系统的一部分。节流由闪存设备外部的逻辑执行，并且包括响应于闪存设备的估计剩余寿命来计算节流因子。确定节流因子是否超过阈值。响应于确定节流因子不超过阈值，将数据写入闪存设备。响应于确定节流因子超过阈值，将数据写入第二存储器件。

4. 发明授权

US08645619B2 Optimized flash based cache memory 失效
公开(公告)号：US08645619B2
公开(公告)日：2014-02-04
申请号：US13553194
申请日：2012-07-19
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotern , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotern , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

5. 发明申请

US20130054873A1 STORAGE SYSTEM CACHE USING FLASH MEMORY WITH DIRECT BLOCK ACCESS 有权
标题翻译：使用具有直接块访问的闪存存储系统缓存
公开(公告)号：US20130054873A1
公开(公告)日：2013-02-28
申请号：US13220256
申请日：2011-08-29
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
IPC分类号： G06F12/02
CPC分类号： G06F12/0866 , G06F2212/222 , G06F2212/262
摘要： Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks.
摘要翻译：本发明的实施例使得包括闪速存储器设备的存储高速缓存具有对闪存的直接块访问，使得物理块地址被呈现给存储系统的高速缓存层，从而控制存储高速缓存数据流。本发明的一个方面包括缓存存储系统。缓存存储系统包括以阵列配置组织的多个闪存单元。多个闪存单元中的每一个包括至少一个闪存设备和闪存单元控制器。每个闪存单元控制器为缓存存储系统提供对其至少一个闪存设备的直接物理块访问。高速缓存存储系统还包括存储高速缓存控制器。存储高速缓存控制器选择要写入数据的要擦除的物理块地址位置，向与所选择的物理块地址位置对应的闪存单元控制器发出擦除命令，并将页写入操作发布到一组擦除块。

6. 发明授权

US08583868B2 Storage system cache using flash memory with direct block access 有权
标题翻译：存储系统缓存使用直接块访问的闪存
公开(公告)号：US08583868B2
公开(公告)日：2013-11-12
申请号：US13220256
申请日：2011-08-29
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
IPC分类号： G06F12/16
CPC分类号： G06F12/0866 , G06F2212/222 , G06F2212/262
摘要： Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks.
摘要翻译：本发明的实施例使得包括闪速存储器设备的存储高速缓存具有对闪存的直接块访问，使得物理块地址被呈现给存储系统的高速缓存层，从而控制存储高速缓存数据流。本发明的一个方面包括缓存存储系统。缓存存储系统包括以阵列配置组织的多个闪存单元。多个闪存单元中的每一个包括至少一个闪存设备和闪存单元控制器。每个闪存单元控制器为缓存存储系统提供对其至少一个闪存设备的直接物理块访问。高速缓存存储系统还包括存储高速缓存控制器。存储高速缓存控制器选择要写入数据的要擦除的物理块地址位置，向与所选择的物理块地址位置对应的闪存单元控制器发出擦除命令，并将页写入操作发布到一组擦除块。

7. 发明申请

US20120221920A1 MULTIPLE ERASURE CORRECTING CODES FOR STORAGE ARRAYS 有权
标题翻译：用于存储阵列的多个擦除修正代码
公开(公告)号：US20120221920A1
公开(公告)日：2012-08-30
申请号：US13036817
申请日：2011-02-28
申请人： Mario Blaum , James L. Hafner , Steven R. Hetzler , Daniel F. Smith
发明人： Mario Blaum , James L. Hafner , Steven R. Hetzler , Daniel F. Smith
IPC分类号： G11C29/00
CPC分类号： G06F11/108 , G11C2029/0411
摘要： Embodiments of the invention relate to erasure correcting codes for storage arrays. An aspect of the invention includes receiving a read stripe from a plurality of storage devices. The read stripe includes a block of pages arranged in rows and columns, with each column corresponding to one of the storage devices. The pages include data pages and parity pages, with the number of parity pages at least one more than the number of rows and not a multiple of the number of rows. The method further includes reconstructing at least one erased page in response to determining that the read stripe includes the at least one erased page and that the number of erased pages is less than or equal to the number of parity pages. The reconstructing is responsive to a multiple erasure correcting code and to the block of pages. The reconstructing results in a recovered read stripe.
摘要翻译：本发明的实施例涉及存储阵列的擦除校正码。本发明的一个方面包括从多个存储设备接收读取条带。读取条带包括以行和列排列的页面块，每一列对应于其中一个存储设备。这些页面包括数据页和奇偶校验页，奇偶校验页的数量至少比行数多一个，而不是行数的倍数。所述方法还包括响应于确定所述读取条带包括所述至少一个已擦除页面并且所述擦除页面的数量小于或等于所述奇偶校验页数来重构至少一个已擦除页面。重建响应于多个擦除校正码和页块。重建导致恢复的读取条带。

8. 发明授权

US09058291B2 Multiple erasure correcting codes for storage arrays 有权
标题翻译：存储阵列的多个擦除校正码
公开(公告)号：US09058291B2
公开(公告)日：2015-06-16
申请号：US13036817
申请日：2011-02-28
申请人： Mario Blaum , James L. Hafner , Steven R. Hetzler , Daniel F. Smith
发明人： Mario Blaum , James L. Hafner , Steven R. Hetzler , Daniel F. Smith
IPC分类号： G11C29/00 , G06F11/10 , G11C29/04
CPC分类号： G06F11/108 , G11C2029/0411
摘要： Embodiments of the invention relate to erasure correcting codes for storage arrays. An aspect of the invention includes receiving a read stripe from a plurality of storage devices. The read stripe includes a block of pages arranged in rows and columns, with each column corresponding to one of the storage devices. The pages include data pages and parity pages, with the number of parity pages at least one more than the number of rows and not a multiple of the number of rows. The method further includes reconstructing at least one erased page in response to determining that the read stripe includes the at least one erased page and that the number of erased pages is less than or equal to the number of parity pages. The reconstructing is responsive to a multiple erasure correcting code and to the block of pages. The reconstructing results in a recovered read stripe.
摘要翻译：本发明的实施例涉及存储阵列的擦除校正码。本发明的一个方面包括从多个存储设备接收读取条带。读取条带包括以行和列排列的页面块，每一列对应于其中一个存储设备。这些页面包括数据页和奇偶校验页，奇偶校验页的数量至少比行数多一个，而不是行数的倍数。所述方法还包括响应于确定所述读取条带包括所述至少一个已擦除页面并且所述擦除页面的数量小于或等于所述奇偶校验页数来重构至少一个已擦除页面。重建响应于多个擦除校正码和页块。重建导致恢复的读取条带。

9. 发明授权

US08006126B2 Data integrity validation in storage systems 失效
标题翻译：存储系统中的数据完整性验证
公开(公告)号：US08006126B2
公开(公告)日：2011-08-23
申请号：US12777446
申请日：2010-05-11
申请人： Veera W. Deenadhayalan , James L. Hafner , James C. Wyllie , Wendy A. Belluomini
发明人： Veera W. Deenadhayalan , James L. Hafner , James C. Wyllie , Wendy A. Belluomini
IPC分类号： G06F11/00
CPC分类号： G06F11/1076 , G06F2211/1007 , G06F2211/104 , G06F2211/109
摘要： Data validation systems and methods are provided. Data is recorded in N data chunks on one or more storage mediums. A first validation chunk independently associated with said N data chunks comprises first validation information for verifying accuracy of data recorded in said N data chunks. The first validation chunk is associated with a first validation appendix comprising second validation information, wherein the first validation appendix is stored on a first storage medium independent of said one or more storage mediums.
摘要翻译：提供数据验证系统和方法。数据记录在一个或多个存储介质上的N个数据块中。独立地与所述N个数据块相关联的第一验证块包括用于验证记录在所述N个数据块中的数据的精度的第一验证信息。第一验证块与包括第二验证信息的第一验证附录相关联，其中第一验证附录存储在独立于所述一个或多个存储介质的第一存储介质上。

10. 发明申请

US20100217752A1 DATA INTEGRITY VALIDATION IN STORAGE SYSTEMS 失效
标题翻译：存储系统中的数据一致性验证
公开(公告)号：US20100217752A1
公开(公告)日：2010-08-26
申请号：US12777446
申请日：2010-05-11
申请人： Veera W. Deenadhayalan , James L. Hafner , James C. Wyllie , Wendy A. Belluomini
发明人： Veera W. Deenadhayalan , James L. Hafner , James C. Wyllie , Wendy A. Belluomini
IPC分类号： G06F17/30
CPC分类号： G06F11/1076 , G06F2211/1007 , G06F2211/104 , G06F2211/109
摘要： Data validation systems and methods are provided. Data is recorded in N data chunks on one or more storage mediums. A first validation chunk independently associated with said N data chunks comprises first validation information for verifying accuracy of data recorded in said N data chunks. The first validation chunk is associated with a first validation appendix comprising second validation information, wherein the first validation appendix is stored on a first storage medium independent of said one or more storage mediums.
摘要翻译：提供数据验证系统和方法。数据记录在一个或多个存储介质上的N个数据块中。独立地与所述N个数据块相关联的第一验证块包括用于验证记录在所述N个数据块中的数据的精度的第一验证信息。第一验证块与包括第二验证信息的第一验证附录相关联，其中第一验证附录存储在独立于所述一个或多个存储介质的第一存储介质上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式