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1. 发明授权

US08006126B2 Data integrity validation in storage systems 失效
标题翻译：存储系统中的数据完整性验证
公开(公告)号：US08006126B2
公开(公告)日：2011-08-23
申请号：US12777446
申请日：2010-05-11
申请人： Veera W. Deenadhayalan , James L. Hafner , James C. Wyllie , Wendy A. Belluomini
发明人： Veera W. Deenadhayalan , James L. Hafner , James C. Wyllie , Wendy A. Belluomini
IPC分类号： G06F11/00
CPC分类号： G06F11/1076 , G06F2211/1007 , G06F2211/104 , G06F2211/109
摘要： Data validation systems and methods are provided. Data is recorded in N data chunks on one or more storage mediums. A first validation chunk independently associated with said N data chunks comprises first validation information for verifying accuracy of data recorded in said N data chunks. The first validation chunk is associated with a first validation appendix comprising second validation information, wherein the first validation appendix is stored on a first storage medium independent of said one or more storage mediums.
摘要翻译：提供数据验证系统和方法。数据记录在一个或多个存储介质上的N个数据块中。独立地与所述N个数据块相关联的第一验证块包括用于验证记录在所述N个数据块中的数据的精度的第一验证信息。第一验证块与包括第二验证信息的第一验证附录相关联，其中第一验证附录存储在独立于所述一个或多个存储介质的第一存储介质上。

2. 发明申请

US20100217752A1 DATA INTEGRITY VALIDATION IN STORAGE SYSTEMS 失效
标题翻译：存储系统中的数据一致性验证
公开(公告)号：US20100217752A1
公开(公告)日：2010-08-26
申请号：US12777446
申请日：2010-05-11
申请人： Veera W. Deenadhayalan , James L. Hafner , James C. Wyllie , Wendy A. Belluomini
发明人： Veera W. Deenadhayalan , James L. Hafner , James C. Wyllie , Wendy A. Belluomini
IPC分类号： G06F17/30
CPC分类号： G06F11/1076 , G06F2211/1007 , G06F2211/104 , G06F2211/109
摘要： Data validation systems and methods are provided. Data is recorded in N data chunks on one or more storage mediums. A first validation chunk independently associated with said N data chunks comprises first validation information for verifying accuracy of data recorded in said N data chunks. The first validation chunk is associated with a first validation appendix comprising second validation information, wherein the first validation appendix is stored on a first storage medium independent of said one or more storage mediums.
摘要翻译：提供数据验证系统和方法。数据记录在一个或多个存储介质上的N个数据块中。独立地与所述N个数据块相关联的第一验证块包括用于验证记录在所述N个数据块中的数据的精度的第一验证信息。第一验证块与包括第二验证信息的第一验证附录相关联，其中第一验证附录存储在独立于所述一个或多个存储介质的第一存储介质上。

3. 发明申请

US20080282105A1 DATA INTEGRITY VALIDATION IN STORAGE SYSTEMS 失效
标题翻译：存储系统中的数据一致性验证
公开(公告)号：US20080282105A1
公开(公告)日：2008-11-13
申请号：US11747188
申请日：2007-05-10
申请人： Veera W. Deenadhayalan , James L. Hafner , James C. Wyllie , Wendy A. Belluomini
发明人： Veera W. Deenadhayalan , James L. Hafner , James C. Wyllie , Wendy A. Belluomini
IPC分类号： G06F11/00
CPC分类号： G06F11/1076 , G06F2211/1007 , G06F2211/104 , G06F2211/109
摘要： Data validation systems and methods are provided. Data is recorded in N data chunks on one or more storage mediums. A first validation chunk independently associated with said N data chunks comprises first validation information for verifying accuracy of data recorded in said N data chunks. The first validation chunk is associated with a first validation appendix comprising second validation information, wherein the first validation appendix is stored on a first storage medium independent of said one or more storage mediums.
摘要翻译：提供数据验证系统和方法。数据记录在一个或多个存储介质上的N个数据块中。独立地与所述N个数据块相关联的第一验证块包括用于验证记录在所述N个数据块中的数据的精度的第一验证信息。第一验证块与包括第二验证信息的第一验证附录相关联，其中第一验证附录存储在与所述一个或多个存储介质无关的第一存储介质上。

4. 发明申请

US20130054873A1 STORAGE SYSTEM CACHE USING FLASH MEMORY WITH DIRECT BLOCK ACCESS 有权
标题翻译：使用具有直接块访问的闪存存储系统缓存
公开(公告)号：US20130054873A1
公开(公告)日：2013-02-28
申请号：US13220256
申请日：2011-08-29
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
IPC分类号： G06F12/02
CPC分类号： G06F12/0866 , G06F2212/222 , G06F2212/262
摘要： Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks.
摘要翻译：本发明的实施例使得包括闪速存储器设备的存储高速缓存具有对闪存的直接块访问，使得物理块地址被呈现给存储系统的高速缓存层，从而控制存储高速缓存数据流。本发明的一个方面包括缓存存储系统。缓存存储系统包括以阵列配置组织的多个闪存单元。多个闪存单元中的每一个包括至少一个闪存设备和闪存单元控制器。每个闪存单元控制器为缓存存储系统提供对其至少一个闪存设备的直接物理块访问。高速缓存存储系统还包括存储高速缓存控制器。存储高速缓存控制器选择要写入数据的要擦除的物理块地址位置，向与所选择的物理块地址位置对应的闪存单元控制器发出擦除命令，并将页写入操作发布到一组擦除块。

5. 发明授权

US08583868B2 Storage system cache using flash memory with direct block access 有权
标题翻译：存储系统缓存使用直接块访问的闪存
公开(公告)号：US08583868B2
公开(公告)日：2013-11-12
申请号：US13220256
申请日：2011-08-29
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
IPC分类号： G06F12/16
CPC分类号： G06F12/0866 , G06F2212/222 , G06F2212/262
摘要： Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks.
摘要翻译：本发明的实施例使得包括闪速存储器设备的存储高速缓存具有对闪存的直接块访问，使得物理块地址被呈现给存储系统的高速缓存层，从而控制存储高速缓存数据流。本发明的一个方面包括缓存存储系统。缓存存储系统包括以阵列配置组织的多个闪存单元。多个闪存单元中的每一个包括至少一个闪存设备和闪存单元控制器。每个闪存单元控制器为缓存存储系统提供对其至少一个闪存设备的直接物理块访问。高速缓存存储系统还包括存储高速缓存控制器。存储高速缓存控制器选择要写入数据的要擦除的物理块地址位置，向与所选择的物理块地址位置对应的闪存单元控制器发出擦除命令，并将页写入操作发布到一组擦除块。

6. 发明授权

US08645619B2 Optimized flash based cache memory 失效
公开(公告)号：US08645619B2
公开(公告)日：2014-02-04
申请号：US13553194
申请日：2012-07-19
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotern , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotern , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

7. 发明授权

US08656088B2 Optimized flash based cache memory 失效
标题翻译：优化基于闪存的高速缓存
公开(公告)号：US08656088B2
公开(公告)日：2014-02-18
申请号：US13112894
申请日：2011-05-20
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotem , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotem , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.
摘要翻译：本发明的实施例涉及对闪存设备的限制访问。闪存设备是包括闪存设备和第二存储设备的存储系统的一部分。节流由闪存设备外部的逻辑执行，并且包括响应于闪存设备的估计剩余寿命来计算节流因子。确定节流因子是否超过阈值。响应于确定节流因子不超过阈值，将数据写入闪存设备。响应于确定节流因子超过阈值，将数据写入第二存储器件。

8. 发明申请

US20120297127A1 OPTIMIZED FLASH BASED CACHE MEMORY 失效
公开(公告)号：US20120297127A1
公开(公告)日：2012-11-22
申请号：US13553194
申请日：2012-07-19
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/02
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

9. 发明申请

US20120297113A1 OPTIMIZED FLASH BASED CACHE MEMORY 失效
标题翻译：优化的基于闪存的高速缓存存储器
公开(公告)号：US20120297113A1
公开(公告)日：2012-11-22
申请号：US13112894
申请日：2011-05-20
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/02
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.
摘要翻译：本发明的实施例涉及对闪存设备的限制访问。闪存设备是包括闪存设备和第二存储设备的存储系统的一部分。节流由闪存设备外部的逻辑执行，并且包括响应于闪存设备的估计剩余寿命来计算节流因子。确定节流因子是否超过阈值。响应于确定节流因子不超过阈值，将数据写入闪存设备。响应于确定节流因子超过阈值，将数据写入第二存储器件。

10. 发明申请

US20110093648A1 ACHIEVING A HIGH THROUGHPUT IN A STORAGE CACHE APPLICATION USING A FLASH SOLID STATE DISK 有权
标题翻译：使用闪存固态盘在存储缓存应用程序中实现高速传输
公开(公告)号：US20110093648A1
公开(公告)日：2011-04-21
申请号：US12603113
申请日：2009-10-21
申请人： Wendy A. Belluomini , Binny S. Gill , Michael A. Ko
发明人： Wendy A. Belluomini , Binny S. Gill , Michael A. Ko
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0868 , G06F12/0246
摘要： According to one embodiment, a method for using flash memory in a storage cache comprises receiving data to be cached in flash memory of a storage cache, at least some of the received data being received from at least one of a host system and a storage medium, selecting a block of the flash memory for receiving the data, buffering the received data until sufficient data has been received to fill the block, and overwriting existing data in the selected block with the buffered data. According to another embodiment, a method comprises receiving data, at least some of the data being from a host system and/or a storage medium, and sequentially overwriting sequential blocks of the flash memory with the received data. Other devices and methods for working with flash memory in a storage cache according to various embodiments are included and described herein.
摘要翻译：根据一个实施例，一种在存储高速缓存中使用闪速存储器的方法包括：接收要存储在存储高速缓存的闪速存储器中的数据，至少一些所接收的数据从主机系统和存储介质中的至少一个接收，选择用于接收数据的闪速存储器块，缓冲接收的数据，直到已经接收到足够的数据来填充块，并用缓冲的数据覆盖所选块中的现有数据。根据另一实施例，一种方法包括接收来自主机系统和/或存储介质的数据中的至少一些数据，并且用接收到的数据顺序地重写闪速存储器的顺序块。本文包括并描述了根据各种实施例的用于处理存储高速缓存中的闪存的其它设备和方法。

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