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1. 发明授权

US06403494B1 Method of forming a floating gate self-aligned to STI on EEPROM 有权
标题翻译：在EEPROM上形成与STI自对准的浮动栅极的方法
公开(公告)号：US06403494B1
公开(公告)日：2002-06-11
申请号：US09638300
申请日：2000-08-14
申请人： Wen-Ting Chu , Di-Son Kuo , Jack Yeh , Chia-Ta Hsieh , Chuan-Li Chang
发明人： Wen-Ting Chu , Di-Son Kuo , Jack Yeh , Chia-Ta Hsieh , Chuan-Li Chang
IPC分类号： H01L2100
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory cell. In a first embodiment, the close self-alignment is made possible through a new use of an anti-reflective coating (ARC) in the various process steps of the making of the cell. In the second embodiment, a low-viscosity material is used in such a manner so as to enable self-alignment of the floating gate to the STI in a simple way.
摘要翻译：公开了一种用于形成分裂栅极闪存单元的方法，其中单元的浮置栅极自对准到浅沟槽隔离（STI），其又使得其自对准到源极和字线。这将有利地影响存储器单元的尺寸的收缩。在第一实施例中，通过在制造电池的各种工艺步骤中新的使用抗反射涂层（ARC）使得紧密的自对准成为可能。在第二实施例中，以这样的方式使用低粘度材料，以便能够以简单的方式使浮动栅极与STI的自对准。

2. 发明授权

US06468863B2 Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof 有权
标题翻译：采用电介质阻挡层的分流栅场效应晶体管（FET）器件及其制造方法
公开(公告)号：US06468863B2
公开(公告)日：2002-10-22
申请号：US09761276
申请日：2001-01-16
申请人： Chia-Ta Hsieh , Di-Son Kuo , Jake Yeh , Chuan-Li Chang , Wen-Ting Chu , Sheng-Wei Tsaur
发明人： Chia-Ta Hsieh , Di-Son Kuo , Jake Yeh , Chuan-Li Chang , Wen-Ting Chu , Sheng-Wei Tsaur
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7885
摘要： Within both a method for fabricating a split gate field effect transistor and the split gate field effect transistor fabricated employing the method, there is employed a patterned silicon nitride barrier dielectric layer formed covering a first portion of a floating gate and a first portion of a semiconductor substrate adjacent the first portion of the floating gate. Within the first portion of the semiconductor substrate there is eventually formed a source/drain region, and more particularly a source region, when fabricating the split gate field effect transistor. The patterned silicon nitride barrier dielectric layer inhibits when fabricating the split gate field effect transistor ion implant damage of the floating gate and oxidative loss of a floating gate electrode edge.
摘要翻译：在制造分裂栅极场效应晶体管的方法和使用该方法制造的分裂栅极场效应晶体管的两者中，采用形成为覆盖浮置栅极的第一部分和半导体的第一部分的图案化氮化硅阻挡介电层衬底邻近浮动栅极的第一部分。在半导体衬底的第一部分内，当制造分裂栅极场效应晶体管时，最终形成源极/漏极区域，尤其是源极区域。图案化的氮化硅阻挡介电层在制造分离栅场效应晶体管离子注入损坏浮栅和浮栅电极边缘的氧化损失时禁止。

3. 发明授权

US06333228B1 Method to improve the control of bird's beak profile of poly in split gate flash 有权
标题翻译：提高分流闸闪光灯中鸟类喙形状控制的方法
公开(公告)号：US06333228B1
公开(公告)日：2001-12-25
申请号：US09534160
申请日：2000-03-24
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Jack Yeh , Wen-Ting Chu , Di-Son Kuo
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Jack Yeh , Wen-Ting Chu , Di-Son Kuo
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A method is provided to improve the control of bird's beak profile of poly in a split gate flash memory cell. The control of the bird's beak profile is achieved in a first embodiment where the polycrystalline layer of the floating gate is annealed at a high temperature. The annealing promotes small grain size and hence smoother surface in the polysilicon, which in turn promotes sharper poly tip. The smoother poly surface also results in thinner inter-poly between the floating gate and the control gate, which together with the sharp poly tip, enhances the erase speed of the split-gate flash memory cell. In a second embodiment, the performance is further enhanced by providing an amorphous silicon for the floating gate, because the amorphous nature of the silicon yields a very smooth surface. This smooth surface is transferred to the recrystallized state of the silicon layer through annealing. Thus, a good control for the bird's beak is achieved. A sharp and short poly tip then results from a well controlled and well-defined bird's beak. Hence, an enhanced split-gate flash memory cell follows.
摘要翻译：提供了一种方法来改善分裂门闪存单元中聚鸟的鸟嘴形状的控制。在第一实施例中实现鸟嘴形状的控制，其中浮栅的多晶层在高温下退火。退火促进了多晶硅中的小晶粒尺寸和因此更平滑的表面，这又促进了更尖锐的多晶硅尖端。更平滑的多晶面也导致浮栅和控制栅之间的更薄的多晶硅，其与尖锐的多晶硅尖端一起增强了分离栅闪存单元的擦除速度。在第二实施例中，通过为浮置栅极提供非晶硅来进一步提高性能，因为硅的无定形性能产生非常光滑的表面。该光滑表面通过退火转移到硅层的再结晶状态。因此，可以很好地控制鸟的喙。然后，一个尖锐和短的多头尖端来自良好控制和明确定义的鸟的喙。因此，增强的分闸式闪存单元如下。

4. 发明授权

US6127229A Process of forming an EEPROM device having a split gate 有权
标题翻译：形成具有分裂栅极的EEPROM器件的工艺
公开(公告)号：US6127229A
公开(公告)日：2000-10-03
申请号：US301222
申请日：1999-04-29
申请人： Wen-Ting Chu , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh , Chia-Ta Hsieh , Yai-Fen Lin
发明人： Wen-Ting Chu , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh , Chia-Ta Hsieh , Yai-Fen Lin
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： There is presented an improved method of fabricating an EEPROM device with a split gate. In the method, a silicon substrate is provided having spaced and parallel recessed oxide regions that isolate component regions where the oxide regions project above the top surface of the substrate. A thin gate oxide is formed on the substrate, and a first conformal layer is deposited over the gate oxide and projecting oxide regions. The substrate is then chemical-mechanically polished to remove the projections of polysilicon over the oxide regions. A silicon nitride layer is deposited on the resultant planar surface of the polysilicon, and elongated openings formed that will define the position of the floating gates that are perpendicular to the oxide regions. The exposed polysilicon in the openings in the silicon nitride are oxidized down to at least the level of the underlying silicon oxide regions, and the silicon nitride layer removed. The polysilicon layer is then removed using the silicon oxide layer as an etch barrier, and the edge surfaces of the resulting polysilicon floating gates oxidized. A second polysilicon layer is deposited on the substrate and elongated word lines formed that are parallel and partially overlapping the floating gates. Source lines are formed in the substrate, and gate lines are formed that overlie the floating gates.
摘要翻译：提出了一种用分裂栅极制造EEPROM器件的改进方法。在该方法中，提供硅衬底，其具有间隔开且平行的凹陷氧化物区域，其隔离氧化物区域突出在衬底的顶表面上方的组分区域。在衬底上形成薄栅氧化物，并且在栅极氧化物和突出的氧化物区域上沉积第一共形层。然后将衬底进行化学机械抛光以去除多晶硅在氧化物区域上的突起。在所形成的多晶硅的平坦表面上沉积氮化硅层，形成将形成垂直于氧化物区域的浮栅的位置的细长开口。氮化硅中的开口中的暴露的多晶硅被氧化到至少下面的氧化硅区域的水平，并且去除了氮化硅层。然后使用氧化硅层作为蚀刻阻挡层去除多晶硅层，并且所得多晶硅浮栅的边缘表面被氧化。第二多晶硅层沉积在衬底上，并且形成平行且部分地与浮动栅极重叠的细长字线。在衬底中形成源极线，并且形成覆盖浮栅的栅极线。

5. 发明授权

US06465836B2 Vertical split gate field effect transistor (FET) device 有权
标题翻译：垂直分流栅场效应晶体管（FET）器件
公开(公告)号：US06465836B2
公开(公告)日：2002-10-15
申请号：US09821199
申请日：2001-03-29
申请人： Chrong Jung Lin , Sheng-Wei Tsao , Di-Son Kuo , Jack Yeh , Wen-Ting Chu , Chung-Li Chang , Chia-Ta Hsieh
发明人： Chrong Jung Lin , Sheng-Wei Tsao , Di-Son Kuo , Jack Yeh , Wen-Ting Chu , Chung-Li Chang , Chia-Ta Hsieh
IPC分类号： H01L29788
CPC分类号： H01L29/7887 , H01L29/42336
摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transistor (FET) device. Similarly, there is also formed within the split gate field effect transistor a floating gate electrode within the trench and covering within the trench a lower sub-portion of the channel region. Finally, the floating gate electrode in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel. The split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.
摘要翻译：在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，在半导体衬底内形成沟槽，其沟槽内的沟槽区域完全包含在分离栅极场内效应晶体管（FET）器件。类似地，在分裂栅极场效应晶体管内还形成有沟槽内的浮置栅电极，并且在沟槽内覆盖沟道区的下部子部分。最后，浮栅电极依次形成在沟槽内垂直和水平重叠的覆盖通道的上部子部分的控制栅电极。分离栅场效应晶体管（FET）器件制造具有增强的面密度和增强的性能。

6. 发明授权

US06544828B1 Adding a poly-strip on isolation's edge to improve endurance of high voltage NMOS on EEPROM 有权
标题翻译：在隔离边缘添加多芯片，以提高EEPROM上高压NMOS的耐用性
公开(公告)号：US06544828B1
公开(公告)日：2003-04-08
申请号：US10044860
申请日：2001-11-07
申请人： Wen-Ting Chu , Di-Son Kuo , Jack Yeh , Chia-Ta Hsieh , Chrong-Jung Lin , Sheng-Wei Tsaur
发明人： Wen-Ting Chu , Di-Son Kuo , Jack Yeh , Chia-Ta Hsieh , Chrong-Jung Lin , Sheng-Wei Tsaur
IPC分类号： H01L218234
CPC分类号： H01L29/402 , H01L21/28123 , H01L21/823481 , H01L29/4238
摘要： A method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is described. Active areas are separated by isolation regions in a substrate. A gate oxide layer is grown on the active areas. A conducting layer is deposited overlying the gate oxide layer and patterned to form gate electrodes in the active areas and to form conductive strips overlapping both the active areas and the isolation areas at an isolation's edge on a drain side of the active areas wherein the conductive strips reduce the electric field at the isolation's edge in the fabrication of an integrated circuit device.
摘要翻译：描述了通过在漏极侧的浅沟槽隔离区域的边缘处形成导电场板来提高高电压NMOS器件的耐久性和鲁棒性的方法。活性区域通过衬底中的隔离区域分离。在活性区域上生长栅极氧化物层。导电层沉积在栅极氧化物层上并被图案化以在有源区域中形成栅电极，并且在有源区域的漏极侧上的隔离边缘处形成与有源区域和隔离区域重叠的导电条带，其中导电条在集成电路器件的制造中减小隔离边缘的电场。

7. 发明授权

US06297099B1 Method to free control tunneling oxide thickness on poly tip of flash 有权
标题翻译：自由控制闪光多头尖端的隧道氧化物厚度的方法
公开(公告)号：US06297099B1
公开(公告)日：2001-10-02
申请号：US09765045
申请日：2001-01-19
申请人： Chia-Ta Hsieh , Di-Son Kuo , Jack Yeh , Chrong Jung Lin , Wen-Ting Chu , Chung-Li Chang
发明人： Chia-Ta Hsieh , Di-Son Kuo , Jack Yeh , Chrong Jung Lin , Wen-Ting Chu , Chung-Li Chang
IPC分类号： H01L218247
CPC分类号： H01L21/28273 , H01L29/42324 , Y10S438/981
摘要： A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion. A polysilicon layer is formed over the interpoly oxide layer. The structure is patterned to form a floating gate/word line device.
摘要翻译：一种制造浮栅/字线装置的方法，包括以下步骤。提供半导体结构。在半导体结构上方形成浮栅部分。浮动门部分具有侧壁和顶面。多晶氧化物部分形成在浮动栅极的顶表面上。在半导体结构，多晶氧化物部分和多晶氧化物部分之上形成多层氧化物层。所述多晶硅氧化物层具有初始厚度，并且包括：与所述浮动栅极部分相邻的所述半导体结构的至少一部分上的字线区域部分; 浮动部分侧壁上的侧壁区域部分; 以及多个氧化物部分上方的顶部。互折层氧化物层的顶部的初始厚度减小到第二厚度，而不会减小多晶氧化物字线区域部分的初始厚度或多余氧化物侧壁区域部分的明显部分。在多晶硅层上形成多晶硅层。将结构图案化以形成浮动栅/字线装置。

8. 发明授权

US06803625B2 Method with trench source to increase the coupling of source to floating gate in split gate flash 有权
公开(公告)号：US06803625B2
公开(公告)日：2004-10-12
申请号：US10627013
申请日：2003-07-25
申请人： Chia-Ta Hsieh , Di Son Kuo , Chrong-Jun Lin , Wen-Ting Chu
发明人： Chia-Ta Hsieh , Di Son Kuo , Chrong-Jun Lin , Wen-Ting Chu
IPC分类号： H01L2978
CPC分类号： H01L27/11521 , H01L27/115
摘要： A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.

9. 发明授权

US06538277B2 Split-gate flash cell 有权
标题翻译：分离式闪存单元
公开(公告)号：US06538277B2
公开(公告)日：2003-03-25
申请号：US09920601
申请日：2001-08-02
申请人： Hung-Cheng Sung , Di-Son Kuo , Chuang-Ke Yeh , Chia-Ta Hsieh , Yai-Fen Lin , Wen-Ting Chu
发明人： Hung-Cheng Sung , Di-Son Kuo , Chuang-Ke Yeh , Chia-Ta Hsieh , Yai-Fen Lin , Wen-Ting Chu
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76895 , H01L21/76897 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.
摘要翻译：公开了一种形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多尖端）的新方法。在不使用厚多晶硅层作为浮动栅极的情况下形成多尖端。这可以通过在多晶硅上形成氧化层并氧化多晶硅的侧壁来实现。由于浮栅的多晶硅的起始厚度相对较薄，所以形成的栅极尖或多尖端也必然是薄且尖锐的。因此，该方法避免了超大规模集成技术的缩小设备中遇到的氧化物薄化问题，提高了EEPROM的快速可编程性和擦除性能。

10. 发明授权

US06534821B2 Structure with protruding source in split-gate flash 有权
公开(公告)号：US06534821B2
公开(公告)日：2003-03-18
申请号：US09927071
申请日：2001-08-10
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-ke Yeh , Wen-Ting Chu , Di-Son Kuo
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-ke Yeh , Wen-Ting Chu , Di-Son Kuo
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.

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