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1. 发明申请

US20110278574A1 ACTIVE DEVICE ARRAY SUBSTRATE AND REPAIRING METHOD THEREOF 有权
标题翻译：主动装置阵列基板及其修复方法
公开(公告)号：US20110278574A1
公开(公告)日：2011-11-17
申请号：US12824237
申请日：2010-06-28
申请人： Wen-Chi Chuang , Chung-Hung Peng , Tung-Tsun Lin , Ya-Ling Kuo
发明人： Wen-Chi Chuang , Chung-Hung Peng , Tung-Tsun Lin , Ya-Ling Kuo
IPC分类号： H01L33/08 , H01J9/50
CPC分类号： H01L27/0296 , H01L2251/568
摘要： An active device array substrate including a substrate, a plurality of pixels, a plurality of signal lines, and a repairing structure is provided. The substrate has a display region and a periphery region. The pixels are arranged on the display region of the substrate as an array. The signal lines are electrically connected to the pixels and are respectively extended from the display region to the periphery region. The repairing structure is disposed at the periphery region, and which includes a first repairing line, a second repairing line, an electrostatic discharge (ESD) releasing line, and an ESD protector. The first repairing line is intersected with one ends of the signal lines and is electrically floated. The ESD protector is connected between the second repairing line and the ESD releasing line, and the ESD protector is overlapped with and electrically insulated from the first repairing line.
摘要翻译：提供了包括衬底，多个像素，多个信号线和修复结构的有源器件阵列衬底。基板具有显示区域和外围区域。像素被布置在基板的显示区域上作为阵列。信号线电连接到像素并且分别从显示区域延伸到外围区域。修复结构设置在周边区域，并且包括第一修复线，第二修复线，静电放电（ESD）释放线和ESD保护器。第一个修理线与信号线的一端相交并电浮动。 ESD保护器连接在第二修理线和ESD释放线之间，并且ESD保护器与第一修复线重叠并与其电绝缘。

2. 发明授权

US08569759B2 Active device array substrate and repairing method thereof 有权
标题翻译：有源器件阵列衬底及其修复方法
公开(公告)号：US08569759B2
公开(公告)日：2013-10-29
申请号：US12824237
申请日：2010-06-28
申请人： Wen-Chi Chuang , Chung-Hung Peng , Tung-Tsun Lin , Ya-Ling Kuo
发明人： Wen-Chi Chuang , Chung-Hung Peng , Tung-Tsun Lin , Ya-Ling Kuo
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00
CPC分类号： H01L27/0296 , H01L2251/568
摘要： An active device array substrate including a substrate, a plurality of pixels, a plurality of signal lines, and a repairing structure is provided. The substrate has a display region and a periphery region. The pixels are arranged on the display region of the substrate as an array. The signal lines are electrically connected to the pixels and are respectively extended from the display region to the periphery region. The repairing structure is disposed at the periphery region, and which includes a first repairing line, a second repairing line, an electrostatic discharge (ESD) releasing line, and an ESD protector. The first repairing line is intersected with one ends of the signal lines and is electrically floated. The ESD protector is connected between the second repairing line and the ESD releasing line, and the ESD protector is overlapped with and electrically insulated from the first repairing line.
摘要翻译：提供了包括衬底，多个像素，多个信号线和修复结构的有源器件阵列衬底。基板具有显示区域和外围区域。像素被布置在基板的显示区域上作为阵列。信号线电连接到像素并且分别从显示区域延伸到外围区域。修复结构设置在周边区域，并且包括第一修复线，第二修复线，静电放电（ESD）释放线和ESD保护器。第一个修理线与信号线的一端相交并电浮动。 ESD保护器连接在第二修理线和ESD释放线之间，并且ESD保护器与第一修复线重叠并与其电绝缘。

3. 发明授权

US06917053B2 Thin film transistor array substrate and photolithography process and design of the mask thereof 有权
标题翻译：薄膜晶体管阵列基板和光刻工艺及其掩模设计
公开(公告)号：US06917053B2
公开(公告)日：2005-07-12
申请号：US10708209
申请日：2004-02-17
申请人： Tai-Yu Kuo , Tung-Tsun Lin , Hsu-Ping Tseng
发明人： Tai-Yu Kuo , Tung-Tsun Lin , Hsu-Ping Tseng
IPC分类号： H01L21/77 , H01L21/84 , H01L27/12 , H01L29/04 , H01L31/036
CPC分类号： H01L27/1288 , G03F7/70475 , H01L27/1296
摘要： A thin film transistor array substrate, a photolithography process and a design of a mask thereof are provided. A photoresist layer is formed on a substrate, and a mask is set above the substrate. Then, the display element area of the mask is blocked in order to perform the exposure process to the photoresist layer. After that, the non-display element area of the mask is blocked in order to perform the exposure process to the photoresist layer. Finally, a development process is performed to pattern the photoresist layer. Wherein a plurality of pixel patterns is formed in the photoresist layer corresponding to the display element area, and a plurality of peripheral circuit patterns and a plurality of stitching pixel pattern are formed in the photoresist layer corresponding to the non-display element area. Moreover, each one of the stitching pixel patterns is connected to the corresponding pixel patterns.
摘要翻译：提供薄膜晶体管阵列基板，光刻工艺及其掩模的设计。在基板上形成光致抗蚀剂层，将掩模设置在基板的上方。然后，阻挡掩模的显示元件区域，以对光致抗蚀剂层进行曝光处理。之后，掩模的非显示元件区域被阻挡，以便对光致抗蚀剂层进行曝光处理。最后，进行显影处理以对光致抗蚀剂层进行图案化。其中在对应于显示元件区域的光致抗蚀剂层中形成多个像素图案，并且在对应于非显示元件区域的光致抗蚀剂层中形成多个外围电路图案和多个缝合像素图案。此外，拼接像素图案中的每一个连接到相应的像素图案。

4. 发明申请

US20050040399A1 [THIN FILM TRANSISTOR ARRAY SUBSTRATE AND PHOTOLITHOGRAPHY PROCESS AND DESIGN OF THE MASK THEREOF] 有权
标题翻译： [薄膜晶体管阵列基板和光刻机的工艺及其掩模的设计]
公开(公告)号：US20050040399A1
公开(公告)日：2005-02-24
申请号：US10708209
申请日：2004-02-17
申请人： Tai-Yu Kuo , Tung-Tsun Lin , Hsu-Ping Tseng
发明人： Tai-Yu Kuo , Tung-Tsun Lin , Hsu-Ping Tseng
IPC分类号： H01L21/77 , H01L21/84 , H01L27/12 , H01L29/04
CPC分类号： H01L27/1288 , G03F7/70475 , H01L27/1296
摘要： A thin film transistor array substrate, a photolithography process and a design of a mask thereof are provided. A photoresist layer is formed on a substrate, and a mask is set above the substrate. Then, the display element area of the mask is blocked in order to perform the exposure process to the photoresist layer. After that, the non-display element area of the mask is blocked in order to perform the exposure process to the photoresist layer. Finally, a development process is performed to pattern the photoresist layer. Wherein a plurality of pixel patterns is formed in the photoresist layer corresponding to the display element area, and a plurality of peripheral circuit patterns and a plurality of stitching pixel pattern are formed in the photoresist layer corresponding to the non-display element area. Moreover, each one of the stitching pixel patterns is connected to the corresponding pixel patterns.
摘要翻译：提供薄膜晶体管阵列基板，光刻工艺及其掩模的设计。在基板上形成光致抗蚀剂层，将掩模设置在基板的上方。然后，阻挡掩模的显示元件区域，以对光致抗蚀剂层进行曝光处理。之后，掩模的非显示元件区域被阻挡，以便对光致抗蚀剂层进行曝光处理。最后，进行显影处理以对光致抗蚀剂层进行图案化。其中在对应于显示元件区域的光致抗蚀剂层中形成多个像素图案，并且在对应于非显示元件区域的光致抗蚀剂层中形成多个外围电路图案和多个缝合像素图案。此外，拼接像素图案中的每一个连接到相应的像素图案。

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