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1. 发明申请

US20050158994A1 PCMO spin-coat deposition 有权
标题翻译： PCMO旋涂沉积
公开(公告)号：US20050158994A1
公开(公告)日：2005-07-21
申请号：US10759468
申请日：2004-01-15
申请人： Wei-Wei Zhuang , Lisa Stecker , Gregory Stecker , Sheng Hsu
发明人： Wei-Wei Zhuang , Lisa Stecker , Gregory Stecker , Sheng Hsu
IPC分类号： C01G45/00 , H01L21/28 , H01L23/62 , H01L27/10 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1683
摘要： A Pr1-XCaXMnO3 (PCMO) spin-coat deposition method for eliminating voids is provided, along with a void-free PCMO film structure. The method comprises: forming a substrate, including a noble metal, with a surface; forming a feature, such as a via or trench, normal with respect to the substrate surface; spin-coating the substrate with acetic acid; spin-coating the substrate with a first, low concentration of PCMO solution; spin-coating the substrate with a second concentration of PCMO solution, having a greater concentration of PCMO than the first concentration; baking and RTA annealing (repeated one to five times); post-annealing; and, forming a PCMO film with a void-free interface between the PCMO film and the underlying substrate surface. The first concentration of PCMO solution has a PCMO concentration in the range of 0.01 to 0.1 moles (M). The second concentration of PCMO solution has a PCMO concentration in the range of 0.2 to 0.5 M.
摘要翻译：提供了一种用于消除空隙的Pr 1-X C 3 Mn 3 O 3（PCMO）旋涂沉积方法，以及无空隙 PCMO薄膜结构。该方法包括：用表面形成包括贵金属的基底; 形成相对于衬底表面正常的特征，例如通孔或沟槽; 用乙酸旋涂底物; 用第一种低浓度的PCMO溶液旋涂底物; 以第二浓度的PCMO溶液旋涂底物，其具有比第一浓度更高浓度的PCMO; 烘烤和RTA退火（重复1〜5次）; 后退火; 并且在PCMO膜和下面的衬底表面之间形成具有无空隙界面的PCMO膜。 PCMO溶液的第一浓度的PCMO浓度范围为0.01至0.1摩尔（M）。 PCMO溶液的第二浓度的PCMO浓度范围为0.2-0.5M。

2. 发明申请

US20070048990A1 Method of buffer layer formation for RRAM thin film deposition 审中-公开
标题翻译： RRAM薄膜沉积缓冲层形成方法
公开(公告)号：US20070048990A1
公开(公告)日：2007-03-01
申请号：US11215520
申请日：2005-08-30
申请人： Wei-Wei Zhuang , Sheng Hsu , David Evans , Tingkai Li , Lawrence Charneski
发明人： Wei-Wei Zhuang , Sheng Hsu , David Evans , Tingkai Li , Lawrence Charneski
IPC分类号： H01L21/3205
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method of buffer layer formation for RRAM thin film deposition includes preparing a substrate; depositing a bottom electrode on the substrate; depositing a thin layer of a transition metal having a multiple valence on the bottom electrode; depositing a layer of metal oxide on the transition metal; depositing a top electrode on the metal oxide; annealing the substrate and the layers formed thereon; and completing the RRAM.
摘要翻译：用于RRAM薄膜沉积的缓冲层形成方法包括制备衬底; 在底物上沉积底部电极; 在底部电极上沉积具有多价的过渡金属的薄层; 在过渡金属上沉积一层金属氧化物; 在金属氧化物上沉积顶部电极; 退火衬底及其上形成的层; 并完成RRAM。

3. 发明申请

US20050245039A1 PCMO thin film with resistance random access memory (RRAM) characteristics 有权
标题翻译：具有电阻随机存取存储器（RRAM）特性的PCMO薄膜
公开(公告)号：US20050245039A1
公开(公告)日：2005-11-03
申请号：US10836689
申请日：2004-04-30
申请人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
发明人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
IPC分类号： C01G45/00 , C01F11/02 , C01F17/00 , C01G99/00 , G11C13/00 , H01L21/00 , H01L21/20 , H01L27/10 , H01L43/08 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1−xCa2+xMnO thin film composition, where 0.1
摘要翻译：已经提供了具有预定的记忆电阻特性和相关的形成过程的PrCaMnO（PCMO）薄膜。在一个方面，所述方法包括：形成Pr 3+ 1-x 2 Ca 2 O 3 x MnO薄膜组成，其中0.1 _0.78Mn^{4+</SUP>_0.22O^2-_{2.96 组合， Mn和O离子的比例变化如下：O 2 - （2.96）; Mn（3+）+（（1-x）+ 8％）; 和Mn 4+（x-8％）。在另一方面，该方法响应于晶体取向在PCMO膜中产生密度。例如，如果PCMO膜具有（110）取向，则在垂直于（110）取向的平面中产生在每平方英尺5至6.76个Mn原子的范围内的密度。}}

4. 发明申请

US20050141269A1 Electrically programmable resistance cross point memory circuit 审中-公开
标题翻译：电可编程电阻交叉点存储电路
公开(公告)号：US20050141269A1
公开(公告)日：2005-06-30
申请号：US11066708
申请日：2005-02-24
申请人： Sheng Hsu , Wei-Wei Zhuang
发明人： Sheng Hsu , Wei-Wei Zhuang
IPC分类号： H01L27/115 , G11C11/15 , G11C11/56 , G11C13/00 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/24 , H01L43/08 , G11C11/00
CPC分类号： G11C11/15 , G11C11/16 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/77 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.
摘要翻译：提供了电阻式交叉点存储器件以及制造和使用方法。存储器件包括插在上电极和下电极之间的钙钛矿材料的有源层。在上电极和下电极的交叉点处位于有源层内的位区域具有响应于施加一个或更多个电压脉冲而可以在值范围内变化的电阻率。可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。提供存储器电路以帮助编程和读出位区域。

5. 发明申请

US20070221975A1 Bipolar switching PCMO capacitor 有权
标题翻译：双极开关PCMO电容
公开(公告)号：US20070221975A1
公开(公告)日：2007-09-27
申请号：US11805177
申请日：2007-05-22
申请人： Tingkai Li , Lawrence Charneski , Wei-Wei Zhuang , David Evans , Sheng Hsu
发明人： Tingkai Li , Lawrence Charneski , Wei-Wei Zhuang , David Evans , Sheng Hsu
IPC分类号： H01L29/92
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1616
摘要： A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.
摘要翻译：提供了多层Pr 1 x 1 x x MnO 3（PCMO）薄膜电容器和相关的沉积方法，用于形成双极开关薄膜。该方法包括：形成底部电极; 沉积纳米晶体PCMO层; 沉积多晶的PCMO层; 形成具有双极开关特性的多层PCMO膜; 并形成覆盖PCMO膜的顶部电极。如果多晶层沉积在纳米晶层之上，则可以用窄脉冲宽度，负电压脉冲写入高电阻。 PCMO膜可以使用窄脉冲宽度，正幅度脉冲复位为低电阻。同样，如果纳米晶层沉积在多晶层上，则可以用窄脉冲宽度，正电压脉冲写入高电阻，并使用窄脉冲宽度，负幅度脉冲将其复位为低电阻。

6. 发明申请

US20060246606A1 Self-aligned cross point resistor memory array 有权
标题翻译：自对准交叉点电阻存储器阵列
公开(公告)号：US20060246606A1
公开(公告)日：2006-11-02
申请号：US11120385
申请日：2005-05-02
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet , Wei-Wei Zhuang
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet , Wei-Wei Zhuang
IPC分类号： H01L21/8234
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.
摘要翻译：制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

7. 发明申请

US20060214172A1 Electroluminescence device with nanotip diodes 有权
标题翻译：具有纳米二极管的电致发光器件
公开(公告)号：US20060214172A1
公开(公告)日：2006-09-28
申请号：US11090386
申请日：2005-03-23
申请人： Sheng Hsu , Tingkai Li , Wei-Wei Zhuang
发明人： Sheng Hsu , Tingkai Li , Wei-Wei Zhuang
IPC分类号： H01L33/00 , H01L21/00
CPC分类号： H01L33/08 , B82Y20/00 , H01L33/18 , H01L33/24 , H01L33/34 , H01L33/502 , Y10S977/834
摘要： A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.
摘要翻译：提供了一种纳米末端电致发光（EL）二极管和一种用于制造所述器件的方法。该方法包括：形成多个Si纳米二极管; 形成覆盖所述纳米二极管的磷光体层; 并且形成覆盖磷光体层的顶部电极。纳米二极管通过以下方式形成：形成具有顶表面的Si衬底; 形成Si对孔; 形成层叠Si层的厚度为30〜300纳米（nm）的Si的n +层; 形成覆盖在衬底顶表面上的反应离子蚀刻（RIE）诱导的聚合物草; 使用RIE诱导的聚合物草作为掩模，蚀刻未被掩模覆盖的基底的区域; 以及在由掩模覆盖的衬底的区域中形成纳米二极管二极管。

8. 发明申请

US20050207265A1 Memory cell with an asymmetric crystalline structure 有权
标题翻译：具有不对称晶体结构的记忆单元
公开(公告)号：US20050207265A1
公开(公告)日：2005-09-22
申请号：US11130983
申请日：2005-05-16
申请人： Sheng Hsu , Tingkai Li , David Evans , Wei-Wei Zhuang , Wei Pan
发明人： Sheng Hsu , Tingkai Li , David Evans , Wei-Wei Zhuang , Wei Pan
IPC分类号： H01L27/10 , G11C11/15 , G11C13/00 , H01L45/00 , G11C8/02
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1625
摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.
摘要翻译：提供了非对称结构的存储单元和制造方法。该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度的第一层。在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

9. 发明申请

US20050054138A1 Method of fabricating trench isolated cross-point memory array 有权
公开(公告)号：US20050054138A1
公开(公告)日：2005-03-10
申请号：US10971263
申请日：2004-10-21
申请人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： G11C11/15 , G11C11/56 , G11C13/00 , H01L27/24 , H01L21/00
CPC分类号： G11C11/15 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/72 , G11C2213/77 , H01L27/24
摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

10. 发明申请

US20050037520A1 Method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer 有权
标题翻译：当与高度结晶的种子层集成时，获得PCMO薄膜上的可逆电阻开关的方法
公开(公告)号：US20050037520A1
公开(公告)日：2005-02-17
申请号：US10640770
申请日：2003-08-13
申请人： Wei-Wei Zhuang , Tingkai Li , David Evans , Sheng Hsu , Wei Pan
发明人： Wei-Wei Zhuang , Tingkai Li , David Evans , Sheng Hsu , Wei Pan
IPC分类号： H01L27/04 , H01L21/20 , H01L21/822 , H01L45/00 , H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.
摘要翻译：当与高度结晶的种子层集成时，用于获得PCMO薄膜上的可逆电阻开关的方法包括通过MOCVD沉积高度结晶形式的PCMO的种子层，薄膜的厚度为约50埃至300埃通过旋转涂覆沉积种子层上的第二PCMO薄膜层，其厚度为约500埃至3000埃以形成组合的PCMO层; 通过施加约-4V至-5V之间的脉冲宽度在约75ns至1个音箱之间的负电脉冲来增加半导体器件中组合的PCMO膜的电阻; 并且通过施加脉冲宽度大于2.0个音箱的约+ 2.5V至+ 4V之间的正电脉冲来降低半导体器件中组合的PCMO层的电阻。

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