会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 7. 发明授权
    • Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays
    • 基于隧道电阻器结的微米级/纳米级解复用器阵列
    • US07319416B2
    • 2008-01-15
    • US11343325
    • 2006-01-30
    • Warren RobinettGregory S. SniderDuncan StewartJoseph Straznicky
    • Warren RobinettGregory S. SniderDuncan StewartJoseph Straznicky
    • H03M7/14
    • G11C8/10G11C13/0023H03M13/51
    • Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address. The encoder-demultiplexer also includes a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal address.
    • 本发明的各种实施例涉及包括隧穿电阻器纳米线结的解复用器,以及纳米线寻址方法,用于在纳米尺度和混合尺度解复用器中可靠地寻址纳米线信号线。 在本发明的一个实施例中,编码器 - 解复用器包括多个输入信号线和一个编码器,其生成在输入信号线上接收的每个不同输入地址的n位恒权重码码字内部地址 。 编码器 - 解复用器包括n个微米级信号线,编码器输出n位恒定权重码码字内部地址,其中每个微信号线承载n位恒权重码内部地址的一位, 代码字内部地址。 编码器 - 解复用器还包括通过隧道电阻器结与n个微米级信号线互连的多个编码器 - 解复用器寻址的纳米线信号线,编码器 - 解复用器寻址的纳米线信号线每个与n比特恒权重信号线相关联, 代码字内部地址。
    • 10. 发明授权
    • Mixed-scale electronic interface
    • 混合电子接口
    • US07692215B2
    • 2010-04-06
    • US11701086
    • 2007-01-31
    • R. Stanley WilliamsGregory S. SniderDuncan Stewart
    • R. Stanley WilliamsGregory S. SniderDuncan Stewart
    • H01L27/10H01L29/73
    • H01L29/0665B82Y10/00G11C2213/81H01H1/0094H01L27/285H01L29/0673H01L29/0676H01L51/0591H01L51/0595
    • Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer. Pins can be configured according to any periodic tiling of the microscale layer.
    • 本发明的实施例涉及包括在集成电路和其他电子设备中的混合比例电子接口,其提供主要是微米级或亚微米级的微尺度特征之间的密集电互连以及主要为纳米尺度层的纳米尺度特征。 在本发明的一个实施方案中,主要是纳米尺度层包括通过平行的,紧密间隔的纳米线束组之间的纳米线结密合地互连的亚微米级或微米级的镶嵌图案。 主要是亚微米级或微尺度层包括与主要是纳米级层中的亚微米级或微尺度焊盘互补定位的引脚。 引脚可以根据微层的任何周期性平铺进行配置。