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1. 发明授权

US08674862B1 Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter 有权
标题翻译：逐次逼近寄存器模数转换器的数字校准系统和方法
公开(公告)号：US08674862B1
公开(公告)日：2014-03-18
申请号：US13604446
申请日：2012-09-05
申请人： Wei Li , Weiqi Ding , Yanjing Ke
发明人： Wei Li , Weiqi Ding , Yanjing Ke
IPC分类号： H03M1/10
CPC分类号： H03M1/1009 , H03M1/00 , H03M1/10 , H03M1/1061 , H03M1/12 , H03M1/38 , H03M1/804
摘要： Systems and methods of calibrating a successive approximation register analog-to-digital converter (ADC) are disclosed. A plurality of capacitor stages, a first capacitor array, and a first capacitor stage are coupled in parallel. A capacitance of the first capacitor stage is compared to a sum of capacitances of the plurality of capacitor stages and of the first capacitor array. In response to the comparing, the capacitance of the first capacitor stage is increased by increasing the capacitance of a second capacitor array if the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.
摘要翻译：公开了校准逐次逼近寄存器模数转换器（ADC）的系统和方法。多个电容器级，第一电容器阵列和第一电容器级并联耦合。将第一电容器级的电容与多个电容器级和第一电容器阵列的电容之和进行比较。响应于比较，如果第一电容器级的电容小于多个电容器级的电容和第一电容器级的电容之和，则通过增加第二电容器阵列的电容来增加第一电容器级的电容电容阵列。

2. 发明授权

US08416001B2 Techniques for reducing duty cycle distortion in periodic signals 有权
标题翻译：降低周期信号中占空比失真的技术
公开(公告)号：US08416001B2
公开(公告)日：2013-04-09
申请号：US13083431
申请日：2011-04-08
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1565 , H03K3/017 , H03K5/12 , H03M9/00
摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.
摘要翻译：发射机电路可操作以响应于第一周期性信号提供输出信号。多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。采样器电路可操作以在第一操作阶段产生所选信号的第一采样。采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

3. 发明授权

US08395421B1 Configurable buffer circuits and methods 有权
标题翻译：可配置缓冲电路和方法
公开(公告)号：US08395421B1
公开(公告)日：2013-03-12
申请号：US13446772
申请日：2012-04-13
申请人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
发明人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
IPC分类号： H03B1/00
CPC分类号： H04L25/0272
摘要： A buffer circuit includes first and second inputs and first and second outputs. The buffer circuit is configurable to buffer a differential input signal received at the first and the second inputs to generate a differential output signal at the first and the second outputs in a current mode logic buffer mode based on a control signal. The buffer circuit is configurable to buffer the differential input signal to generate the differential output signal in an H-bridge buffer mode based on the control signal.
摘要翻译：缓冲电路包括第一和第二输入以及第一和第二输出。缓冲电路可配置为缓冲在第一和第二输入处接收的差分输入信号，以在基于控制信号的当前模式逻辑缓冲器模式中在第一和第二输出处产生差分输出信号。缓冲电路可配置为基于控制信号缓冲差分输入信号以产生H桥缓冲器模式中的差分输出信号。

4. 发明申请

US20120256670A1 Techniques for Reducing Duty Cycle Distortion in Periodic Signals 有权
标题翻译：降低周期信号占空比变形的技术
公开(公告)号：US20120256670A1
公开(公告)日：2012-10-11
申请号：US13083431
申请日：2011-04-08
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Yanjing Ke
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K3/017 , H03K5/12 , H03M9/00
摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.
摘要翻译：发射机电路可操作以响应于第一周期性信号提供输出信号。多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。采样器电路可操作以在第一操作阶段产生所选信号的第一采样。采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

5. 发明授权

US08174294B1 Configurable buffer circuits and methods 有权
标题翻译：可配置缓冲电路和方法
公开(公告)号：US08174294B1
公开(公告)日：2012-05-08
申请号：US12910177
申请日：2010-10-22
申请人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
发明人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
IPC分类号： H03B1/00
CPC分类号： H04L25/0272
摘要： A buffer circuit includes a current source circuit, first and second switch circuits that are coupled to the current source circuit, a first resistor coupled to the first switch circuit, a second resistor coupled to the second switch circuit, and a third switch circuit coupled to the first and the second resistors. The third switch circuit couples the first and the second resistors to a node at a first voltage when the buffer circuit is configured to function in a current mode logic buffer mode. The third switch circuit couples the first and the second resistors to a node at a second voltage when the buffer circuit is configured to function in an H-bridge buffer mode.
摘要翻译：缓冲电路包括电流源电路，耦合到电流源电路的第一和第二开关电路，耦合到第一开关电路的第一电阻器，耦合到第二开关电路的第二电阻器和耦合到第二开关电路的第三开关电路，第一和第二电阻。当缓冲电路被配置为以当前模式逻辑缓冲器模式工作时，第三开关电路将第一和第二电阻器耦合到第一电压的节点。当缓冲电路被配置为以H桥缓冲器模式工作时，第三开关电路将第一和第二电阻器耦合到第二电压的节点。

6. 发明申请

US20080320324A1 Data recovery (CDR) architecture using interpolator and timing loop module 有权
标题翻译：数据恢复（CDR）架构，使用内插器和定时循环模块
公开(公告)号：US20080320324A1
公开(公告)日：2008-12-25
申请号：US11823002
申请日：2007-06-25
申请人： Yanjing Ke , Jianbin Hao , Ning Zhu
发明人： Yanjing Ke , Jianbin Hao , Ning Zhu
IPC分类号： G06F1/12 , G06F1/04 , G06F5/06
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0812 , H04L7/0008 , H04L7/0025
摘要： The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period.
摘要翻译：本发明提供一种使用内插器和定时环模块以及数据锁存电路的相位同步时钟进行数据恢复的方法和机制。内插器可以被认为是在时钟周期内具有指定的延迟分辨率的可编程延迟电路。

7. 发明申请

US20080111919A1 Multiplexed DVI and displayport transmitter 审中-公开
标题翻译：多路复用DVI和显示端口发射机
公开(公告)号：US20080111919A1
公开(公告)日：2008-05-15
申请号：US11598921
申请日：2006-11-13
申请人： Jianbin Hao , Yanjing Ke , Ning Zhu
发明人： Jianbin Hao , Yanjing Ke , Ning Zhu
IPC分类号： H04N7/04 , H04N5/38
CPC分类号： G09G5/005 , G06F3/14 , G06F3/147 , G06F3/153 , G09G3/2092 , G09G3/2096 , G09G5/006
摘要： A semiconductor device that can be used to process and transmit data in two dissimilar formats. DVI or DisplayPort (DPortV1) standardized formats are disclosed. This integration, which can be operated in each mode as fully compliant circuit with the specific standard, allows the same video capture and analog circuits to be configured and used for processing of both formats, thereby reducing the number of circuits required as well as the over all size of the integrated solution. Board space is also reduced by using this integrated chip. The use of the same chip in both applications also takes advantage of the manufacturing economy of scale to reduce the cost of the chip to the customer.
摘要翻译：可用于以两种不同格式处理和传输数据的半导体器件。 DVI或DisplayPort（DPortV 1）标准化格式被公开。该集成可以在每个模式下作为具有特定标准的完全兼容电路运行，允许将相同的视频捕获和模拟电路配置和用于两种格式的处理，从而减少所需的电路数量以及超过所有尺寸的集成解决方案。使用该集成芯片也减少了电路板空间。在两种应用中使用相同的芯片也可以利用规模的制造经济来降低芯片对客户的成本。

8. 发明申请

US20080191760A1 PLLS covering wide operating frequency ranges 有权
标题翻译： PLLS涵盖了广泛的工作频率范围
公开(公告)号：US20080191760A1
公开(公告)日：2008-08-14
申请号：US11707778
申请日：2007-02-12
申请人： Jianbin Hao , Ning Zhu , Yanjing Ke
发明人： Jianbin Hao , Ning Zhu , Yanjing Ke
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/0891 , H03L7/099
摘要： The present invention provides a method and mechanism for adapting a single phase-locked loop (PLL) for a wider range of frequencies than has been possible with prior art solutions. An analog comparator circuit that senses the output of the charge pump voltage and provides an signal to a control circuit to choose a suitable load circuit for the PLL voltage controlled oscillator (VCO). This analog comparator with the digital control circuit is used to cause a change in the VCO loads, from a multiplicity of loads, and select the best VCO range to achieve the incoming signal frequency lock. The use of a single PLL with the analog comparator output to control the VCO load selection, in addition to the phase and frequency feedback of the prior art, allows multiple overlapping frequency ranges of the multiple tunable loads of the VCO to be covered with one PLL. This reduces the die size and power consumption compared to a circuit implementation using the standard PLL for the wider frequency range of operation.
摘要翻译：本发明提供了一种用于适应比现有技术解决方案可能的更宽范围频率的单个锁相环（PLL）的方法和机制。一个模拟比较器电路，用于检测电荷泵电压的输出，并向控制电路提供一个信号，为PLL压控振荡器（VCO）选择合适的负载电路。这种具有数字控制电路的模拟比较器用于从多个负载引起VCO负载的变化，并选择最佳VCO范围以实现输入信号频率锁定。除了现有技术的相位和频率反馈之外，使用具有模拟比较器输出的单个PLL来控制VCO负载选择，允许VCO的多个可调谐负载的多个重叠频率范围被一个PLL覆盖。与使用标准PLL的电路实现相比，在更宽的频率范围内，这降低了管芯尺寸和功耗。

9. 发明申请

US20080117984A1 Pre-Clock/Data Recovery Multiplexing of Input Signals in a HDMI Video Receiver 审中-公开
标题翻译：输入信号在HDMI视频接收机中的预时钟/数据恢复复用
公开(公告)号：US20080117984A1
公开(公告)日：2008-05-22
申请号：US11869592
申请日：2007-10-09
申请人： Jianbin Hao , Ning Zhu , Yanjing Ke
发明人： Jianbin Hao , Ning Zhu , Yanjing Ke
IPC分类号： H03K5/159
CPC分类号： H04N5/765 , G09G5/006 , G09G2370/12 , H04N21/436
摘要： High Definition Multimedia Interface (HDMI) receivers use digital multiplexer at the input stage after equalization, clock and data recovery for each channel of each port. Described herein is the use of an analog multiplexer for HDMI receiver. The purpose of the analog multiplexer is to reduce the die size and power consumption by selecting the input signal from one port out of a set of input ports, right after the equalization and hence use only one block of clock and data recovery (CDR) circuits for the receiver. This sharing of one block of CDR circuits between all input ports requires the use of analog multiplexer circuits, as the signals presented to the analog multiplexer after equalization are of low signal strength and have insufficient signal-to-noise ratio to allow handling by digital multiplexer circuitry.
摘要翻译：高分辨率多媒体接口（HDMI）接收机在每个端口的每个通道的均衡，时钟和数据恢复之后的输入级使用数字多路复用器。这里描述的是使用HDMI接收器的模拟多路复用器。模拟多路复用器的目的是通过从均衡之后的一组输入端口中的一个端口选择输入信号来减少芯片尺寸和功耗，因此仅使用一个时钟和数据恢复（CDR）电路块为接收器。在所有输入端口之间共享CDR电路的一个块需要使用模拟多路复用器电路，因为在均衡之后呈现给模拟多路复用器的信号具有低信号强度并且具有不足的信噪比以允许数字多路复用器电路。

10. 发明授权

US07861105B2 Clock data recovery (CDR) system using interpolator and timing loop module 有权
标题翻译：使用内插器和定时循环模块的时钟数据恢复（CDR）系统
公开(公告)号：US07861105B2
公开(公告)日：2010-12-28
申请号：US11823002
申请日：2007-06-25
申请人： Yanjing Ke , Jianbin Hao , Ning Zhu
发明人： Yanjing Ke , Jianbin Hao , Ning Zhu
IPC分类号： G06F1/12 , G06F11/00
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0812 , H04L7/0008 , H04L7/0025
摘要： The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period.
摘要翻译：本发明提供一种使用内插器和定时环模块以及数据锁存电路的相位同步时钟进行数据恢复的方法和机制。内插器可以被认为是在时钟周期内具有指定的延迟分辨率的可编程延迟电路。

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