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1. 发明申请

US20080117984A1 Pre-Clock/Data Recovery Multiplexing of Input Signals in a HDMI Video Receiver 审中-公开
标题翻译：输入信号在HDMI视频接收机中的预时钟/数据恢复复用
公开(公告)号：US20080117984A1
公开(公告)日：2008-05-22
申请号：US11869592
申请日：2007-10-09
申请人： Jianbin Hao , Ning Zhu , Yanjing Ke
发明人： Jianbin Hao , Ning Zhu , Yanjing Ke
IPC分类号： H03K5/159
CPC分类号： H04N5/765 , G09G5/006 , G09G2370/12 , H04N21/436
摘要： High Definition Multimedia Interface (HDMI) receivers use digital multiplexer at the input stage after equalization, clock and data recovery for each channel of each port. Described herein is the use of an analog multiplexer for HDMI receiver. The purpose of the analog multiplexer is to reduce the die size and power consumption by selecting the input signal from one port out of a set of input ports, right after the equalization and hence use only one block of clock and data recovery (CDR) circuits for the receiver. This sharing of one block of CDR circuits between all input ports requires the use of analog multiplexer circuits, as the signals presented to the analog multiplexer after equalization are of low signal strength and have insufficient signal-to-noise ratio to allow handling by digital multiplexer circuitry.
摘要翻译：高分辨率多媒体接口（HDMI）接收机在每个端口的每个通道的均衡，时钟和数据恢复之后的输入级使用数字多路复用器。这里描述的是使用HDMI接收器的模拟多路复用器。模拟多路复用器的目的是通过从均衡之后的一组输入端口中的一个端口选择输入信号来减少芯片尺寸和功耗，因此仅使用一个时钟和数据恢复（CDR）电路块为接收器。在所有输入端口之间共享CDR电路的一个块需要使用模拟多路复用器电路，因为在均衡之后呈现给模拟多路复用器的信号具有低信号强度并且具有不足的信噪比以允许数字多路复用器电路。

2. 发明申请

US20080320324A1 Data recovery (CDR) architecture using interpolator and timing loop module 有权
标题翻译：数据恢复（CDR）架构，使用内插器和定时循环模块
公开(公告)号：US20080320324A1
公开(公告)日：2008-12-25
申请号：US11823002
申请日：2007-06-25
申请人： Yanjing Ke , Jianbin Hao , Ning Zhu
发明人： Yanjing Ke , Jianbin Hao , Ning Zhu
IPC分类号： G06F1/12 , G06F1/04 , G06F5/06
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0812 , H04L7/0008 , H04L7/0025
摘要： The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period.
摘要翻译：本发明提供一种使用内插器和定时环模块以及数据锁存电路的相位同步时钟进行数据恢复的方法和机制。内插器可以被认为是在时钟周期内具有指定的延迟分辨率的可编程延迟电路。

3. 发明申请

US20080111919A1 Multiplexed DVI and displayport transmitter 审中-公开
标题翻译：多路复用DVI和显示端口发射机
公开(公告)号：US20080111919A1
公开(公告)日：2008-05-15
申请号：US11598921
申请日：2006-11-13
申请人： Jianbin Hao , Yanjing Ke , Ning Zhu
发明人： Jianbin Hao , Yanjing Ke , Ning Zhu
IPC分类号： H04N7/04 , H04N5/38
CPC分类号： G09G5/005 , G06F3/14 , G06F3/147 , G06F3/153 , G09G3/2092 , G09G3/2096 , G09G5/006
摘要： A semiconductor device that can be used to process and transmit data in two dissimilar formats. DVI or DisplayPort (DPortV1) standardized formats are disclosed. This integration, which can be operated in each mode as fully compliant circuit with the specific standard, allows the same video capture and analog circuits to be configured and used for processing of both formats, thereby reducing the number of circuits required as well as the over all size of the integrated solution. Board space is also reduced by using this integrated chip. The use of the same chip in both applications also takes advantage of the manufacturing economy of scale to reduce the cost of the chip to the customer.
摘要翻译：可用于以两种不同格式处理和传输数据的半导体器件。 DVI或DisplayPort（DPortV 1）标准化格式被公开。该集成可以在每个模式下作为具有特定标准的完全兼容电路运行，允许将相同的视频捕获和模拟电路配置和用于两种格式的处理，从而减少所需的电路数量以及超过所有尺寸的集成解决方案。使用该集成芯片也减少了电路板空间。在两种应用中使用相同的芯片也可以利用规模的制造经济来降低芯片对客户的成本。

4. 发明申请

US20080191760A1 PLLS covering wide operating frequency ranges 有权
标题翻译： PLLS涵盖了广泛的工作频率范围
公开(公告)号：US20080191760A1
公开(公告)日：2008-08-14
申请号：US11707778
申请日：2007-02-12
申请人： Jianbin Hao , Ning Zhu , Yanjing Ke
发明人： Jianbin Hao , Ning Zhu , Yanjing Ke
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/0891 , H03L7/099
摘要： The present invention provides a method and mechanism for adapting a single phase-locked loop (PLL) for a wider range of frequencies than has been possible with prior art solutions. An analog comparator circuit that senses the output of the charge pump voltage and provides an signal to a control circuit to choose a suitable load circuit for the PLL voltage controlled oscillator (VCO). This analog comparator with the digital control circuit is used to cause a change in the VCO loads, from a multiplicity of loads, and select the best VCO range to achieve the incoming signal frequency lock. The use of a single PLL with the analog comparator output to control the VCO load selection, in addition to the phase and frequency feedback of the prior art, allows multiple overlapping frequency ranges of the multiple tunable loads of the VCO to be covered with one PLL. This reduces the die size and power consumption compared to a circuit implementation using the standard PLL for the wider frequency range of operation.
摘要翻译：本发明提供了一种用于适应比现有技术解决方案可能的更宽范围频率的单个锁相环（PLL）的方法和机制。一个模拟比较器电路，用于检测电荷泵电压的输出，并向控制电路提供一个信号，为PLL压控振荡器（VCO）选择合适的负载电路。这种具有数字控制电路的模拟比较器用于从多个负载引起VCO负载的变化，并选择最佳VCO范围以实现输入信号频率锁定。除了现有技术的相位和频率反馈之外，使用具有模拟比较器输出的单个PLL来控制VCO负载选择，允许VCO的多个可调谐负载的多个重叠频率范围被一个PLL覆盖。与使用标准PLL的电路实现相比，在更宽的频率范围内，这降低了管芯尺寸和功耗。

5. 发明授权

US07861105B2 Clock data recovery (CDR) system using interpolator and timing loop module 有权
标题翻译：使用内插器和定时循环模块的时钟数据恢复（CDR）系统
公开(公告)号：US07861105B2
公开(公告)日：2010-12-28
申请号：US11823002
申请日：2007-06-25
申请人： Yanjing Ke , Jianbin Hao , Ning Zhu
发明人： Yanjing Ke , Jianbin Hao , Ning Zhu
IPC分类号： G06F1/12 , G06F11/00
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0812 , H04L7/0008 , H04L7/0025
摘要： The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period.
摘要翻译：本发明提供一种使用内插器和定时环模块以及数据锁存电路的相位同步时钟进行数据恢复的方法和机制。内插器可以被认为是在时钟周期内具有指定的延迟分辨率的可编程延迟电路。

6. 发明授权

US07692497B2 PLLS covering wide operating frequency ranges 有权
标题翻译： PLLS涵盖了广泛的工作频率范围
公开(公告)号：US07692497B2
公开(公告)日：2010-04-06
申请号：US11707778
申请日：2007-02-12
申请人： Jianbin Hao , Ning Zhu , Yanjing Ke
发明人： Jianbin Hao , Ning Zhu , Yanjing Ke
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0891 , H03L7/099
摘要： The present invention provides a method and mechanism for adapting a single phase-locked loop (PLL) for a wider range of frequencies than has been possible with prior art solutions. An analog comparator circuit that senses the output of a charge pump and provides a signal to a digital control circuit to choose a suitable load circuit for the PLL voltage controlled oscillator (VCO). The analog comparator with the digital control circuit changes the VCO loads to select the best VCO range to achieve the incoming signal frequency lock. A single PLL with the VCO load selection method disclosed, with use of built-in hysteresis, in addition to the phase and frequency feedback of the prior art, allows multiple overlapping frequency ranges to be covered in a stable fashion. This enables frequency locking of the PLL over a wide range of frequencies with a small die size and low power consumption.
摘要翻译：本发明提供了一种用于适应比现有技术解决方案可能的更宽范围频率的单个锁相环（PLL）的方法和机制。模拟比较器电路，用于检测电荷泵的输出，并向数字控制电路提供信号，为PLL压控振荡器（VCO）选择合适的负载电路。具有数字控制电路的模拟比较器改变VCO负载，以选择最佳VCO范围来实现输入信号频率锁定。除了现有技术的相位和频率反馈之外，利用内置迟滞公开的具有VCO负载选择方法的单个PLL允许以稳定的方式覆盖多个重叠的频率范围。这使得PLL能够在较小的芯片尺寸和低功耗的宽范围的频率上锁定PLL。

7. 发明授权

US08269897B2 Method and apparatus for video format conversion 有权
标题翻译：用于视频格式转换的方法和装置
公开(公告)号：US08269897B2
公开(公告)日：2012-09-18
申请号：US11869600
申请日：2007-10-09
申请人： Jianbin Hao , Ning Zhu
发明人： Jianbin Hao , Ning Zhu
IPC分类号： H04N9/67
CPC分类号： H04N7/01 , G06F7/766 , H03K19/1737
摘要： High-Definition Multimedia Interface Specification, Version 1.2, supports multiple video formats. Currently the HDMI sources and sinks support multiple formats through reconfiguration of the system. The present invention describes the use of a configurable ‘n’×‘n’ data pixel mapping matrix for video format conversion. This mapping matrix allows the mapping of any existing video format to any other existing or future video format and allows flexibility of connectivity to any transmitter or receiver. Accordingly a more user friendly implementation that provides greater flexibility for development and use of new formats in video applications is shown.
摘要翻译：高清多媒体接口规范1.2版支持多种视频格式。目前，HDMI源和接收器通过重新配置系统来支持多种格式。本发明描述了用于视频格式转换的可配置“n”×n“数据像素映射矩阵的使用。该映射矩阵允许将任何现有视频格式映射到任何其他现有或将来的视频格式，并允许与任何发射机或接收机的连接的灵活性。因此，显示了更加用户友好的实现，其为视频应用中的新格式的开发和使用提供了更大的灵活性。

8. 发明申请

US20080174693A1 Method and Apparatus for Video Format Conversion 有权
标题翻译：视频格式转换的方法和装置
公开(公告)号：US20080174693A1
公开(公告)日：2008-07-24
申请号：US11869600
申请日：2007-10-09
申请人： Jianbin Hao , Ning Zhu
发明人： Jianbin Hao , Ning Zhu
IPC分类号： H04N7/01
CPC分类号： H04N7/01 , G06F7/766 , H03K19/1737
摘要： High-Definition Multimedia Interface Specification, Version 1.2, supports multiple video formats. Currently the HDMI sources and sinks support multiple formats through reconfiguration of the system. The present invention describes the use of a configurable ‘n’×‘n’ data pixel mapping matrix for video format conversion. This mapping matrix allows the mapping of any existing video format to any other existing or future video format and allows flexibility of connectivity to any transmitter or receiver. Accordingly a more user friendly implementation that provides greater flexibility for development and use of new formats in video applications is shown.
摘要翻译：高清多媒体接口规范1.2版支持多种视频格式。目前，HDMI源和接收器通过重新配置系统来支持多种格式。本发明描述了用于视频格式转换的可配置“n”x“数据像素映射矩阵的使用。该映射矩阵允许将任何现有视频格式映射到任何其他现有或将来的视频格式，并允许与任何发射机或接收机的连接的灵活性。因此，显示了更加用户友好的实现，其为视频应用中的新格式的开发和使用提供了更大的灵活性。

9. 发明授权

US07602806B2 Signaling and coding methods and apparatus for long-range 10 and 100 MBPS ethernet transmission 有权
标题翻译：用于长距离10和100 MBPS以太网传输的信号和编码方法和装置
公开(公告)号：US07602806B2
公开(公告)日：2009-10-13
申请号：US11005686
申请日：2004-12-07
申请人： Kewei Yang , Jianbin Hao , Fei Yao , Ning Zhu
发明人： Kewei Yang , Jianbin Hao , Fei Yao , Ning Zhu
IPC分类号： H04L12/28 , H04J3/16 , H04B1/66
CPC分类号： H04L5/1446 , H04L25/03885 , H04L25/4917
摘要： Signaling and coding methods and apparatus for long-range 10 and 100 mbps Ethernet transmission. In accordance with the method, a physical layer (PHY) device is provided that includes the long-range capabilities. In operation, the PHY measures the distance to a companion PHY, and if it is within the specification limits, communicates with the companion device in the normal way. If the distance is above the specification limits, the PHY checks to see if the companion PHY is similarly enabled, and if so, switches to a long-range signaling method. In a preferred embodiment, NRZ coding with pre-emphasis on the first bit of two or more bits of the same value is used for a first range exceeding the specification limit, and PAM4 coding is used for a second range exceeding the first range. Various embodiments are disclosed.
摘要翻译：用于长距离10和100 mbps以太网传输的信号和编码方法和装置。根据该方法，提供了包括远程能力的物理层（PHY）设备。在操作中，PHY测量到伴侣PHY的距离，如果它在规范限制内，则以正常方式与配套设备进行通信。如果距离超过规范限制，则PHY会检查伴侣PHY是否类似地启用，如果是，则切换到远程信令方式。在优选实施例中，对于超过规格限制的第一范围使用具有相同值的两个或更多位的第一比特的预加重的NRZ编码，并且在超过第一范围的第二范围中使用PAM4编码。公开了各种实施例。

10. 发明申请

US20080239082A1 HDMI format video pattern and audio frequencies generator for field test and built-in self test 审中-公开
标题翻译： HDMI格式视频格式和音频发生器，用于现场测试和内置自检
公开(公告)号：US20080239082A1
公开(公告)日：2008-10-02
申请号：US11731607
申请日：2007-03-29
申请人： Ning Zhu , Jianbin Hao
发明人： Ning Zhu , Jianbin Hao
IPC分类号： H04N17/00
CPC分类号： H04N17/00 , G01R31/3167 , G01R31/3187
摘要： A versatile video pattern and audio pattern generation module, that can be integrated onto a video integrated circuit (IC) to generate functional video test input data, in HDMI format, for gray bars, color bars and moving bar data patterns, and to further generate single-tone audio signals, is disclosed. This video signal generator can be made part of the built-in-self test (BIST) to allow simplified testing of the IC. The signals generated can be used to test the video and audio functionality, as well as enabling a system to be demonstrated in the field. The output of the generator during the demonstration can be displayed using any suitable video display enabling simplified demonstration set-up. These video and audio signals can bemused as a diagnostic tool by the consumer and also for debugging the IC and system as may be necessary.
摘要翻译：一种通用的视频图案和音频图案生成模块，可以集成到视频集成电路（IC）上，以HDMI格式生成功能视频测试输入数据，用于灰色条，彩条和移动条数据模式，并进一步生成公开了单音音频信号。该视频信号发生器可以作为内置自检（BIST）的一部分，以便简化IC的测试。所产生的信号可用于测试视频和音频功能，以及使系统能够在现场得到证明。演示期间发生器的输出可以使用任何合适的视频显示进行显示，从而实现简化的演示设置。这些视频和音频信号可以作为消费者的诊断工具，并且可能需要调试IC和系统。

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