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1. 发明申请

US20060125470A1 System and method for IDDQ measurement in system on a chip (SOC) design 有权
标题翻译：系统芯片（SOC）设计中IDDQ测量的系统和方法
公开(公告)号：US20060125470A1
公开(公告)日：2006-06-15
申请号：US11010135
申请日：2004-12-10
申请人： Wei Chen , Hugh Mair , Uming Ko , David Scott
发明人： Wei Chen , Hugh Mair , Uming Ko , David Scott
IPC分类号： G01R31/28
CPC分类号： G01R31/3008 , G01R31/3012
摘要： System and method for detecting transistor failure in large-scale integrated circuits by measuring IDDQ. A preferred embodiment comprises a switch structure for an integrated circuit made up of a plurality of main switches (such as main switch 410) selectively coupling a power sub-domain to a power source pin, a plurality of pi-switches (such as pi-switch 415) selectively coupling pairs of power sub-domains, and a plurality of IDDQ switches (such as IDDQ switch 425) selectively coupling the power sub-domains to a VIDDQ pin. The pi-switches can decouple the power sub-domains while the IDDQ switches can enable the measurement of the quiescent current in the power sub-domains. The use of pi-switches and IDDQ switches can permit the measurement of the quiescent current in the power sub-domains without requiring the use of isolation buffers and needed to powering on and off the integrated circuit between current measurements in the different power sub-domains.
摘要翻译：通过测量IDDQ来检测大型集成电路中的晶体管故障的系统和方法。优选实施例包括由多个选择性地将电源子域耦合到电源引脚的多个主开关（例如主开关410）构成的集成电路的开关结构，多个pi开关（例如，开关415）选择性地耦合功率子域对，以及选择性地将功率子域耦合到VIDDQ引脚的多个IDDQ开关（例如IDDQ开关425）。 pi开关可以对功率子域进行去耦，而IDDQ开关可以测量电源子域中的静态电流。 pi开关和IDDQ开关的使用可以允许测量电源子域中的静态电流，而不需要使用隔离缓冲器，并且需要在不同功率子域中的电流测量之间为集成电路供电和关断。

2. 发明授权

US07180208B2 Switch structure for reduced voltage fluctuation in power domains and sub-domains 有权
标题翻译：电源域和子域电压波动减小的开关结构
公开(公告)号：US07180208B2
公开(公告)日：2007-02-20
申请号：US10735943
申请日：2003-12-15
申请人： Wei Chen , Hugh Mair , Uming Ko , David Scott
发明人： Wei Chen , Hugh Mair , Uming Ko , David Scott
IPC分类号： H01H35/00 , H02B1/24
CPC分类号： G06F1/305 , H02J1/08 , H02J2001/008 , Y10T307/391 , Y10T307/766
摘要： System and method for reducing voltage fluctuations in an integrated circuit with multiple power domains and sub-domains. A preferred embodiment comprises a plurality of voltage sources and a switching network (such as switching network 320) wherein outputs from the plurality of voltage sources are inputs. The switching network can couple the outputs of voltage sources (based on a mapping) with the same output voltage levels to reduce voltage fluctuation amongst power domains coupled to the coupled outputs. The coupling may be performed by a switching structure (such as the switching structure 215) that can controllably electrically couple two outputs.
摘要翻译：用于减少具有多个电源域和子域的集成电路中的电压波动的系统和方法。优选实施例包括多个电压源和交换网络（例如交换网络320），其中来自多个电压源的输出是输入。开关网络可以将电压源的输出（基于映射）耦合到相同的输出电压电平，以减少耦合到耦合输出的功率域之间的电压波动。耦合可以由可控制地电耦合两个输出的开关结构（例如开关结构215）来执行。

3. 发明申请

US20050146228A1 Switch structure for reduced voltage fluctuation in power domains and sub-domains 有权
标题翻译：电源域和子域电压波动减小的开关结构
公开(公告)号：US20050146228A1
公开(公告)日：2005-07-07
申请号：US10735943
申请日：2003-12-15
申请人： Wei Chen , Hugh Mair , Uming Ko , David Scott
发明人： Wei Chen , Hugh Mair , Uming Ko , David Scott
IPC分类号： G06F1/30 , H02B1/24 , H02J1/08
CPC分类号： G06F1/305 , H02J1/08 , H02J2001/008 , Y10T307/391 , Y10T307/766
摘要： System and method for reducing voltage fluctuations in an integrated circuit with multiple power domains and sub-domains. A preferred embodiment comprises a plurality of voltage sources and a switching network (such as switching network 320) wherein outputs from the plurality of voltage sources are inputs. The switching network can couple the outputs of voltage sources (based on a mapping) with the same output voltage levels to reduce voltage fluctuation amongst power domains coupled to the coupled outputs. The coupling may be performed by a switching structure (such as the switching structure 215) that can controllably electrically couple two outputs.
摘要翻译：用于减少具有多个电源域和子域的集成电路中的电压波动的系统和方法。优选实施例包括多个电压源和交换网络（例如交换网络320），其中来自多个电压源的输出是输入。开关网络可以将电压源的输出（基于映射）耦合到相同的输出电压电平，以减少耦合到耦合输出的功率域之间的电压波动。耦合可以由可控制地电耦合两个输出的开关结构（例如开关结构215）来执行。

4. 发明申请

US20060267654A1 Ultra low area overhead retention flip-flop for power-down applications 有权
公开(公告)号：US20060267654A1
公开(公告)日：2006-11-30
申请号：US11138788
申请日：2005-05-26
申请人： Sumanth Gururajarao , Hugh Mair , David Scott , Uming Ko
发明人： Sumanth Gururajarao , Hugh Mair , David Scott , Uming Ko
IPC分类号： H03K3/356
CPC分类号： H03K3/356008 , H04W52/0283 , Y02D70/122
摘要： In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.

5. 发明申请

US20070223294A1 Fast access memory architecture 有权
标题翻译：快速访问内存架构
公开(公告)号：US20070223294A1
公开(公告)日：2007-09-27
申请号：US11385151
申请日：2006-03-21
申请人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David Scott , Uming Ko , Alice Wang
发明人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David Scott , Uming Ko , Alice Wang
IPC分类号： G11C7/00
CPC分类号： G11C8/10
摘要： A computer system comprising a control logic and a storage coupled to the control logic. The storage comprises a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.
摘要翻译：一种包括控制逻辑和耦合到控制逻辑的存储器的计算机系统。存储器包括用于在控制逻辑和位单元之间传送数据的多个比特单元和位线。控制逻辑向存储器提供目标位单元的地址。在单个时钟周期内，存储器使用地址来激活目标比特单元，以预先耦合到目标比特单元的位线，并访问目标比特单元。

6. 发明授权

US07162652B2 Integrated circuit dynamic parameter management in response to dynamic energy evaluation 有权
标题翻译：集成电路动态参数管理响应动态能量评估
公开(公告)号：US07162652B2
公开(公告)日：2007-01-09
申请号：US10739469
申请日：2003-12-18
申请人： Sami Issa , Uming Ko , Baher Haroun , David Scott
发明人： Sami Issa , Uming Ko , Baher Haroun , David Scott
IPC分类号： G06F1/00 , G06F1/32 , G01R31/02
CPC分类号： G06F1/3243 , G06F1/3203 , G06F1/3296 , Y02D10/152 , Y02D10/172
摘要： A power management system (12) in an electronic device (10). The system comprises circuitry (14x), responsive to at least one system parameter, for providing data processing functionality, where the circuitry for providing data processing functionality comprises a data path (CPx). The system alternatively or cumulatively also comprises circuitry (22x) for indicating a potential capability of operational speed of the data path and/or circuitry (24x) for indicating an amount of current leakage of the circuitry for providing data processing functionality. The system also comprises circuitry (26) for adjusting the at least one system parameter in response to either or both of the circuitry for indicating a potential capability and the circuitry for indicating an amount of current leakage.
摘要翻译：电子设备（10）中的电源管理系统（12）。响应于至少一个系统参数，该系统包括用于提供数据处理功能的电路（14XX），其中用于提供数据处理功能的电路包括数据路径（CP SUB>）。该系统可替代地或累积地还包括用于指示用于指示数量的数据路径和/或电路（24×x×）的操作速度的潜在能力的电路（22XX）用于提供数据处理功能的电路的电流泄漏。该系统还包括用于响应于用于指示潜在能力的电路中的一个或两者以及用于指示电流泄漏量的电路来调整至少一个系统参数的电路（26）。

7. 发明授权

US07519925B2 Integrated circuit with dynamically controlled voltage supply 有权
标题翻译：具有动态控制电压供应的集成电路
公开(公告)号：US07519925B2
公开(公告)日：2009-04-14
申请号：US11139452
申请日：2005-05-27
申请人： Sami Issa , Uming Ko , David Scott
发明人： Sami Issa , Uming Ko , David Scott
IPC分类号： G06F17/50
CPC分类号： G01R31/3004 , G06F17/5063
摘要： An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability. In selected instances, the circuitry for adjusting adjusts the voltage supplied by the voltage supply to be a voltage greater than the predetermined voltage operating limit while still complying with the predicted lifespan.
摘要翻译：电子系统（10）。该系统包括用于从电压源接收系统电压的电路（P1）。系统还包括响应系统电压的用于提供数据处理功能的电路（141）。用于提供数据处理功能的电路包括关键路径（CP1），并且关键路径包括多个晶体管。多个晶体管中的至少一些晶体管具有对应于预测寿命的相应的预定电压工作极限。该系统还包括用于指示关键路径的操作速度的潜在能力的电路（221）。该系统还包括用于将系统电压耦合到关键路径的电路（CB）。最后，该系统还包括用于响应于用于指示潜在能力的电路来调节由电压源提供的系统电压的电路（26）。在选择的情况下，用于调整的电路将电压供应提供的电压调整为大于预定电压工作极限的电压，同时仍然符合预期的使用寿命。

8. 发明申请

US20070046362A1 Adaptive voltage control and body bias for performance an energy optimization 有权
标题翻译：自适应电压控制和体偏置性能优化
公开(公告)号：US20070046362A1
公开(公告)日：2007-03-01
申请号：US11213477
申请日：2005-08-26
申请人： Gordon Gammie , Alice Wang , Uming Ko , David Scott
发明人： Gordon Gammie , Alice Wang , Uming Ko , David Scott
IPC分类号： H03K3/01
CPC分类号： H03K19/0008 , H03K19/00384
摘要： A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.
摘要翻译：一种用于自适应地控制提供给设备附近的电路的电压的装置，包括耦合到处理模块的处理模块和第一跟踪元件。第一跟踪元件产生指示与电路相关联的第一估计速度的第一值。该装置还包括耦合到处理模块的第二跟踪元件。第二跟踪元件产生指示与电路相关联的第二估计速度的第二值。处理模块将第一和第二值中的每一个与各自的目标值进行比较，并且基于比较使得电压输出被调整。第一和第二跟踪元件包括多个晶体管，至少一些晶体管选择性地提供晶体管偏置电压以调整晶体管速度。

9. 发明申请

US20050273742A1 Integrated circuit with dynamically controlled voltage supply 有权
标题翻译：具有动态控制电压供应的集成电路
公开(公告)号：US20050273742A1
公开(公告)日：2005-12-08
申请号：US11139452
申请日：2005-05-27
申请人： Sami Issa , Uming Ko , David Scott
发明人： Sami Issa , Uming Ko , David Scott
IPC分类号： G06F9/45
CPC分类号： G01R31/3004 , G06F17/5063
摘要： An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability. In selected instances, the circuitry for adjusting adjusts the voltage supplied by the voltage supply to be a voltage greater than the predetermined voltage operating limit while still complying with the predicted lifespan.
摘要翻译：电子系统（10）。该系统包括用于从电压源接收系统电压的电路（P 1 SUB）。该系统还包括响应于系统电压的用于提供数据处理功能的电路（14 1 1）。用于提供数据处理功能的电路包括关键路径（CP <1> 1），并且关键路径包括多个晶体管。多个晶体管中的至少一些晶体管具有对应于预测寿命的相应的预定电压工作极限。该系统还包括用于指示关键路径的操作速度的潜在能力的电路（22I 1）。该系统还包括用于将系统电压耦合到关键路径的电路（CB）。最后，该系统还包括用于响应于用于指示潜在能力的电路来调节由电压源提供的系统电压的电路（26）。在选择的情况下，用于调整的电路将电压供应提供的电压调整为大于预定电压工作极限的电压，同时仍然符合预期的使用寿命。

10. 发明申请

US20060033525A1 Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors 有权
标题翻译：具有低泄漏PMOS和高泄漏NMOS晶体管的集成标头开关
公开(公告)号：US20060033525A1
公开(公告)日：2006-02-16
申请号：US10916135
申请日：2004-08-11
申请人： Hugh Mair , David Scott , Rolf Lagerquist
发明人： Hugh Mair , David Scott , Rolf Lagerquist
IPC分类号： H03K19/003
CPC分类号： H03K17/6872 , H03K19/0013 , H03K19/00315 , H03K2217/0036
摘要： System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.
摘要翻译：为集成电路中的电路提供大的导通电流和小的截止电流的系统和方法。优选实施例包括用于向由PMOS晶体管和并联的NMOS晶体管制成的集成电路中的电路提供功率的开关。每个晶体管的栅极端子耦合到单独的控制信号线。 PMOS晶体管以高电压电源电平向电路提供电流，而NMOS晶体管以低电压电源电平向电路提供电流，其中可以在设计期间改变PMOS和NMOS晶体管的尺寸以满足功率需求。根据功率要求，可以使用多个PMOS和NMOS晶体管。 PMOS和NMOS晶体管的组合允许使用有限的制造工艺，其中可以限制晶体管宽度。

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