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1. 发明授权

US07519925B2 Integrated circuit with dynamically controlled voltage supply 有权
标题翻译：具有动态控制电压供应的集成电路
公开(公告)号：US07519925B2
公开(公告)日：2009-04-14
申请号：US11139452
申请日：2005-05-27
申请人： Sami Issa , Uming Ko , David Scott
发明人： Sami Issa , Uming Ko , David Scott
IPC分类号： G06F17/50
CPC分类号： G01R31/3004 , G06F17/5063
摘要： An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability. In selected instances, the circuitry for adjusting adjusts the voltage supplied by the voltage supply to be a voltage greater than the predetermined voltage operating limit while still complying with the predicted lifespan.
摘要翻译：电子系统（10）。该系统包括用于从电压源接收系统电压的电路（P1）。系统还包括响应系统电压的用于提供数据处理功能的电路（141）。用于提供数据处理功能的电路包括关键路径（CP1），并且关键路径包括多个晶体管。多个晶体管中的至少一些晶体管具有对应于预测寿命的相应的预定电压工作极限。该系统还包括用于指示关键路径的操作速度的潜在能力的电路（221）。该系统还包括用于将系统电压耦合到关键路径的电路（CB）。最后，该系统还包括用于响应于用于指示潜在能力的电路来调节由电压源提供的系统电压的电路（26）。在选择的情况下，用于调整的电路将电压供应提供的电压调整为大于预定电压工作极限的电压，同时仍然符合预期的使用寿命。

2. 发明授权

US07197733B2 Integrated circuit dynamic parameter management in response to dynamic energy evaluation 有权
标题翻译：集成电路动态参数管理响应动态能量评估
公开(公告)号：US07197733B2
公开(公告)日：2007-03-27
申请号：US11456600
申请日：2006-07-11
申请人： Sami Issa , Baher Haroun , Shakti S Rath
发明人： Sami Issa , Baher Haroun , Shakti S Rath
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5063 , G06F17/5031 , G06F2217/86
摘要： A single integrated circuit (12). The integrated circuit comprises a first circuit (14x) having a data path, the first circuit consisting of a first number of logic gates for performing a plurality of logic functions. The integrated circuit also comprises a circuit (22x) for indicating a potential speed capability of the data path. The circuit for indicating comprises a second number of logic gates (82, 92) for performing the plurality of logic functions, wherein the second number is less than the first number. The circuit for indicating also comprises additional circuitry (88, 98) for representing parasitic characteristics in the data path.
摘要翻译：单个集成电路（12）。集成电路包括具有数据路径的第一电路（14），第一电路由用于执行多个逻辑功能的第一数量的逻辑门组成。该集成电路还包括用于指示数据路径的潜在速度能力的电路（22×X）。用于指示的电路包括用于执行多个逻辑功能的第二数量的逻辑门（82,92），其中第二个数字小于第一个数字。用于指示的电路还包括用于表示数据路径中的寄生特性的附加电路（88,98）。

3. 发明申请

US20050273742A1 Integrated circuit with dynamically controlled voltage supply 有权
标题翻译：具有动态控制电压供应的集成电路
公开(公告)号：US20050273742A1
公开(公告)日：2005-12-08
申请号：US11139452
申请日：2005-05-27
申请人： Sami Issa , Uming Ko , David Scott
发明人： Sami Issa , Uming Ko , David Scott
IPC分类号： G06F9/45
CPC分类号： G01R31/3004 , G06F17/5063
摘要： An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability. In selected instances, the circuitry for adjusting adjusts the voltage supplied by the voltage supply to be a voltage greater than the predetermined voltage operating limit while still complying with the predicted lifespan.
摘要翻译：电子系统（10）。该系统包括用于从电压源接收系统电压的电路（P 1 SUB）。该系统还包括响应于系统电压的用于提供数据处理功能的电路（14 1 1）。用于提供数据处理功能的电路包括关键路径（CP <1> 1），并且关键路径包括多个晶体管。多个晶体管中的至少一些晶体管具有对应于预测寿命的相应的预定电压工作极限。该系统还包括用于指示关键路径的操作速度的潜在能力的电路（22I 1）。该系统还包括用于将系统电压耦合到关键路径的电路（CB）。最后，该系统还包括用于响应于用于指示潜在能力的电路来调节由电压源提供的系统电压的电路（26）。在选择的情况下，用于调整的电路将电压供应提供的电压调整为大于预定电压工作极限的电压，同时仍然符合预期的使用寿命。

4. 发明授权

US06947350B2 Synchronous controlled, self-timed local SRAM block 有权
标题翻译：同步控制，自定时本地SRAM块
公开(公告)号：US06947350B2
公开(公告)日：2005-09-20
申请号：US10712383
申请日：2003-11-12
申请人： Gil I. Winograd , Esin Terzioglu , Ali Anvar , Sami Issa
发明人： Gil I. Winograd , Esin Terzioglu , Ali Anvar , Sami Issa
IPC分类号： G06F13/40 , G11C5/06 , G11C7/06 , G11C7/10 , G11C7/18 , G11C7/22 , G11C8/00 , G11C8/10 , G11C11/413 , G11C11/419 , G11C29/00
CPC分类号： G11C11/419 , G06F13/4086 , G11C5/025 , G11C5/06 , G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/41 , G11C11/412 , G11C11/413 , G11C29/808 , G11C29/848
摘要： The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier. One embodiment of the present invention relates to a memory device comprising a plurality of synchronous controlled global elements and a plurality of self-timed local elements. In this embodiment, at least one of the self-timed local elements interfaces with the synchronous controlled global element.
摘要翻译：本发明涉及同步自定时存储装置。该装置包括形成单元阵列的多个存储单元，与单元阵列接口的至少一个本地解码器，至少一个本地读出放大器和至少一个本地控制器。本地感测放大器至少与解码器和单元阵列接口，并且适于对与其耦合的至少一条线进行预充电和均衡。本地控制器与至少本地解码器和读出放大器的活动接口并进行协调。本发明的一个实施例涉及包括多个同步受控全局元件和多个自定时局部元件的存储器件。在该实施例中，自定时局部元件中的至少一个与同步控制的全局元件接口。

5. 发明授权

US06906946B2 Compact and highly efficient DRAM cell 有权
标题翻译：紧凑高效的DRAM单元
公开(公告)号：US06906946B2
公开(公告)日：2005-06-14
申请号：US10657848
申请日：2003-09-09
申请人： Sami Issa
发明人： Sami Issa
IPC分类号： G11C11/404 , G11C11/405 , G11C11/24
CPC分类号： G11C11/404 , G11C11/405
摘要： A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.
摘要翻译：公开了一种紧凑的动态随机存取存储器（DRAM）单元和用于使用DRAM单元的高效方法。 DRAM单元提供ASIC芯片上的数据位的读取，写入和存储。 DRAM单元包括用作通过栅极并具有第一源极节点，第一栅极节点和第一漏极节点的第一晶体管。 DRAM单元还包括用作存储装置的第二晶体管，并且具有电连接到第一漏极节点以形成存储节点的第二漏极节点。第二晶体管还包括第二源极节点和第二栅极节点。第二源节点是电浮动的，从而增加存储节点的有效存储电容。

6. 发明授权

US06882591B2 Synchronous controlled, self-timed local SRAM block 有权
标题翻译：同步控制，自定时本地SRAM块
公开(公告)号：US06882591B2
公开(公告)日：2005-04-19
申请号：US10692230
申请日：2003-10-23
申请人： Gil I. Winograd , Esin Terzioglu , Ali Anvar , Sami Issa
发明人： Gil I. Winograd , Esin Terzioglu , Ali Anvar , Sami Issa
IPC分类号： G06F13/40 , G11C5/06 , G11C7/06 , G11C7/10 , G11C7/18 , G11C7/22 , G11C8/00 , G11C8/10 , G11C11/413 , G11C11/419 , G11C29/00
CPC分类号： G11C11/419 , G06F13/4086 , G11C5/025 , G11C5/06 , G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/41 , G11C11/412 , G11C11/413 , G11C29/808 , G11C29/848
摘要： The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. One embodiment relates to a memory device comprising a muxing device and at least one cluster device coupled to the muxing device. Another embodiment comprises a method of performing at least one of a read and write operation in a memory device. The method comprises activating at least one cluster device in the memory device and firing at least one sense amp in the at least one cluster device.
摘要翻译：本发明涉及同步自定时存储装置。该装置包括形成单元阵列的多个存储单元，与单元阵列接口的至少一个本地解码器，至少一个本地读出放大器和至少一个本地控制器。一个实施例涉及包括多路复用器件和耦合到复用器件的至少一个集群器件的存储器件。另一个实施例包括执行存储器件中的读取和写入操作中的至少一个的方法。该方法包括激活存储器设备中的至少一个集群设备并且激发至少一个集群设备中的至少一个感测放大器。

7. 发明授权

US06650572B2 Compact analog-multiplexed global sense amplifier for rams 有权
标题翻译：紧凑型模拟多路复用全局读出放大器
公开(公告)号：US06650572B2
公开(公告)日：2003-11-18
申请号：US10224841
申请日：2002-08-21
申请人： Sami Issa
发明人： Sami Issa
IPC分类号： G11C1604
CPC分类号： G11C11/4097 , G11C7/1006 , G11C7/12 , G11C7/18 , G11C2207/002 , G11C2207/104
摘要： The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. As a result, the respective local sense amplifiers for the non-selected global bit lines will just read and refresh the respective memory cells. This new approach results in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers). In one embodiment, eight global bit lines are shared by one global sense amplifier and multiplexed to achieve the advantages of the present invention. Due to an analog global multiplexing scheme used by the present invention, only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global bit line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development. The global bit line pairs with no voltage development generate zero voltage development on the local bit lines and the respective activated sense amplifiers amplify only the cell data which reassembles a read and refresh operation.
摘要翻译：本发明的方法和系统通过将未选择的全局位线连接到Vdd来叠加读写操作。结果，用于非选择的全局位线的各个本地读出放大器将仅读取和刷新相应的存储器单元。这种新方法导致较小的本地读出放大器和用于多个存储器单元（和局部读出放大器）的一个全局读出放大器。在一个实施例中，八个全局位线由一个全局读出放大器共享并被多路复用以实现本发明的优点。由于本发明使用的模拟全局复用方案，在写入操作期间，只有一个全局位线对产生作为相应局部读出放大器的输入的电压开发，而另外三个全局位线对与它们各自的本地感测放大器，因此没有电压发展。没有电压开发的全局位线对在局部位线上产生零电压显影，并且相应的激活的读出放大器仅放大重新组合读取和刷新操作的单元数据。

8. 发明授权

US06646954B2 Synchronous controlled, self-timed local SRAM block 有权
标题翻译：同步控制，自定时本地SRAM块
公开(公告)号：US06646954B2
公开(公告)日：2003-11-11
申请号：US10100757
申请日：2002-03-19
申请人： Gil I. Winograd , Esin Terzioglu , Ali Anvar , Sami Issa
发明人： Gil I. Winograd , Esin Terzioglu , Ali Anvar , Sami Issa
IPC分类号： G11C800
CPC分类号： G11C11/419 , G06F13/4086 , G11C5/025 , G11C5/06 , G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/41 , G11C11/412 , G11C11/413 , G11C29/808 , G11C29/848
摘要： The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.
摘要翻译：本发明涉及同步自定时存储装置。该装置包括形成单元阵列的多个存储单元，与单元阵列接口的至少一个本地解码器，至少一个本地读出放大器和至少一个本地控制器。本地感测放大器至少与解码器和单元阵列接口，并且适于对与其耦合的至少一条线进行预充电和均衡。本地控制器与至少本地解码器和读出放大器的活动接口并进行协调。

9. 发明授权

US06480424B1 Compact analog-multiplexed global sense amplifier for RAMS 有权
标题翻译：用于RAMS的紧凑型模拟多路复用全局读出放大器
公开(公告)号：US06480424B1
公开(公告)日：2002-11-12
申请号：US09976236
申请日：2001-10-12
申请人： Sami Issa
发明人： Sami Issa
IPC分类号： G11C1604
CPC分类号： G11C11/4097 , G11C7/1006 , G11C7/12 , G11C7/18 , G11C2207/002 , G11C2207/104
摘要： The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. The respective local sense amplifiers for the non-selected global bit lines just read and refresh the respective memory cells resulting in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers). In one embodiment, eight global bit lines are shared by one global sense amplifier and are multiplexed. Only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global bit line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development. Thus, the respective activated sense amplifiers amplify only the cell data which reassembles a read and refresh operation.
摘要翻译：本发明的方法和系统通过将未选择的全局位线连接到Vdd来叠加读写操作。用于未选择的全局位线的相应的局部读出放大器刚刚读取和刷新相应的存储器单元，导致较小的本地读出放大器和用于多个存储器单元（和局部读出放大器）的一个全局读出放大器。在一个实施例中，八个全局位线由一个全局读出放大器共享并被复用。只有一个全局位线对在写入操作期间产生作为相应局部读出放大器的输入的电压开发，而另外三个全局位线对与其相应的本地读出放大器断开连接，因此没有电压发展。因此，相应的激活的读出放大器仅放大重新组合读取和刷新操作的单元数据。

10. 发明申请

US20090080235A1 COMPACT AND HIGHLY EFFICIENT DRAM CELL 有权
标题翻译：紧凑，高效的DRAM单元
公开(公告)号：US20090080235A1
公开(公告)日：2009-03-26
申请号：US12323283
申请日：2008-11-25
申请人： Sami Issa
发明人： Sami Issa
IPC分类号： G11C11/24 , H01L27/108
CPC分类号： G11C11/404 , G11C11/405
摘要： A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.
摘要翻译：公开了一种紧凑的动态随机存取存储器（DRAM）单元和用于使用DRAM单元的高效方法。 DRAM单元提供ASIC芯片上的数据位的读取，写入和存储。 DRAM单元包括用作通过栅极并具有第一源极节点，第一栅极节点和第一漏极节点的第一晶体管。 DRAM单元还包括用作存储装置的第二晶体管，并且具有电连接到第一漏极节点以形成存储节点的第二漏极节点。第二晶体管还包括第二源极节点和第二栅极节点。第二源节点是电浮动的，从而增加存储节点的有效存储电容。

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