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1. 发明授权

US06185646B2 Method and apparatus for transferring data on a synchronous multi-drop 失效
标题翻译：用于在同步多点传送数据的方法和装置
公开(公告)号：US06185646B2
公开(公告)日：2001-02-06
申请号：US08984611
申请日：1997-12-03
申请人： Wayne Melvin Barrett , Gerald Keith Bartley , Douglas A. Baska , Paul Eric Dahlen , Robert Allen Drehmel , Kenneth Claude Hinz , James Anthony Marcella
发明人： Wayne Melvin Barrett , Gerald Keith Bartley , Douglas A. Baska , Paul Eric Dahlen , Robert Allen Drehmel , Kenneth Claude Hinz , James Anthony Marcella
IPC分类号： G06F1300
CPC分类号： G06F13/1663
摘要： A data transfer method and apparatus are provided for transferring data in a computer system on a high-speed synchronous multi-drop bus. Multiple devices including at least a first group of a plurality of devices and a second group of at least one device are connected to the high-speed synchronous multi-drop bus. To transfer data between devices in the first group, a first unidirectional data valid signal is applied to each device in the second group. The data from a sending device in the first group is transferred to a designated device in the second group. A second unidirectional data valid signal is applied to each device in the first group. The data is transferred from the designated device in the second group to a selected device in the first group.
摘要翻译：提供了一种用于在高速同步多点总线上的计算机系统中传送数据的数据传送方法和装置。包括至少第一组多个设备的多个设备和至少一个设备的第二组连接到高速同步多点总线。为了在第一组中的设备之间传输数据，第一组中的每个设备应用第一单向数据有效信号。来自第一组中的发送设备的数据被传送到第二组中的指定设备。对第一组中的每个设备应用第二单向数据有效信号。数据从第二组中的指定设备传送到第一组中的所选设备。

2. 发明授权

US07254663B2 Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes 有权
标题翻译：具有菊花链通信链路的多节点架构可配置为以单向和双向模式运行
公开(公告)号：US07254663B2
公开(公告)日：2007-08-07
申请号：US10897341
申请日：2004-07-22
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Robert Allen Drehmel , James Anthony Marcella
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Robert Allen Drehmel , James Anthony Marcella
IPC分类号： G06F11/00
CPC分类号： G06F13/364 , G06F11/2007 , G06F11/201
摘要： A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many instances communications may be maintained with nodes located both before and after a discontinuity in a daisy chain configuration.
摘要翻译：电路装置，方法和装置利用可选地配置为在单向和双向模式中操作的通信链路，以在菊花链配置中彼此互连的多个节点之间传送数据。结果，在许多情况下，可以维持在菊花链配置中的不连续之前和之后的节点的通信。

3. 发明授权

US07873773B2 Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes 失效
标题翻译：具有菊花链通信链路的多节点架构可配置为以单向和双向模式运行
公开(公告)号：US07873773B2
公开(公告)日：2011-01-18
申请号：US11740640
申请日：2007-04-26
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Robert Allen Drehmel , James Anthony Marcella
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Robert Allen Drehmel , James Anthony Marcella
IPC分类号： G06F13/14 , G06F13/00 , H04L12/28
CPC分类号： G06F13/364 , G06F11/2007 , G06F11/201
摘要： A circuit arrangement, method and apparatus utilize communication links that are selectively configurable to operate in both unidirectional and bidirectional modes to communicate data between multiple nodes that are interconnected to one another in a daisy chain configuration. As a result, in many instances communications may be maintained with nodes located both before and after a discontinuity in a daisy chain configuration.
摘要翻译：电路装置，方法和装置利用可选地配置为在单向和双向模式中操作的通信链路，以在菊花链配置中彼此互连的多个节点之间传送数据。结果，在许多情况下，可以维持在菊花链配置中的不连续之前和之后的节点的通信。

4. 发明授权

US06513091B1 Data routing using status-response signals 失效
标题翻译：使用状态响应信号的数据路由
公开(公告)号：US06513091B1
公开(公告)日：2003-01-28
申请号：US09439586
申请日：1999-11-12
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
IPC分类号： G06F1314
CPC分类号： G06F13/14
摘要： A method and apparatus for routing data between bus devices, where each bus device is connected to a centralized switch via a point-to-point bus connection. The plurality of point-to-point bus connections collectively form a system bus. After a command is issued on the system bus, each bus device responds to the issued command by transmitting an address status response to a response combining logic module. The response combining logic module identifies which of the bus devices responded with a positive acknowledgment to the issued command, then forwards a device identifier of the bus device responding with the positive acknowledgment to the switch. The switch uses the device identifier returned via the response combining logic to route the data transfer associated with the issued command.
摘要翻译：一种用于在总线设备之间路由数据的方法和设备，其中每个总线设备经由点到点总线连接连接到集中式交换机。多个点到点总线连接共同形成系统总线。在系统总线上发出命令之后，每个总线设备通过向响应组合逻辑模块发送地址状态响应来响应发出的命令。响应组合逻辑模块识别哪个总线设备对所发出的命令进行肯定确认响应，然后将响应于肯定确认的总线设备的设备标识符转发给交换机。交换机使用通过响应组合逻辑返回的设备标识符来路由与发出的命令相关联的数据传输。

5. 发明授权

US06505306B1 Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initialization 失效
标题翻译：冗余位转向机制，在冗余设备初始化期间具有提取操作的延迟切换
公开(公告)号：US06505306B1
公开(公告)日：2003-01-07
申请号：US09396973
申请日：1999-09-15
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
IPC分类号： H02H305
CPC分类号： G11C29/76
摘要： An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.
摘要翻译：装置，程序产品和方法通过将非初始化获取操作从故障存储器设备切换到冗余存储器设备来初始化冗余存储器件，直到冗余存储器件的初始化完成为止。因此，在初始化期间，非初始化提取操作被定向到故障存储器设备，而非初始化存储操作被引导到冗余设备。

6. 发明授权

US07234017B2 Computer system architecture for a processor connected to a high speed bus transceiver 有权
标题翻译：用于连接到高速总线收发器的处理器的计算机系统架构
公开(公告)号：US07234017B2
公开(公告)日：2007-06-19
申请号：US11064745
申请日：2005-02-24
申请人： Giora Biran , Matthew Adam Cushing , Robert Allen Drehmel , Allen James Gavin , Mark E. Kautzman , Jamie Randall Kuesel , Ming-I Mark Lin , David Arnold Luick , James Anthony Marcella , Mark Owen Maxson , Eric Oliver Mejdrich , Adam James Muff , Clarence Rosser Ogilvie , Charles S. Woodruff
发明人： Giora Biran , Matthew Adam Cushing , Robert Allen Drehmel , Allen James Gavin , Mark E. Kautzman , Jamie Randall Kuesel , Ming-I Mark Lin , David Arnold Luick , James Anthony Marcella , Mark Owen Maxson , Eric Oliver Mejdrich , Adam James Muff , Clarence Rosser Ogilvie , Charles S. Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4059
摘要： A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.
摘要翻译：高速计算机处理器系统具有用于图形处理器的高速接口。优选实施例将来自国际商业机器公司（IBM）的称为Giga-Processor Ultralite（GPUL）110的PowerPC微处理器与多芯片模块上的高速接口相结合。

7. 发明授权

US06188627B1 Method and system for improving DRAM subsystem performance using burst refresh control 失效
标题翻译：使用突发刷新控制来提高DRAM子系统性能的方法和系统
公开(公告)号：US06188627B1
公开(公告)日：2001-02-13
申请号：US09374200
申请日：1999-08-13
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , William Paul Hovis , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , William Paul Hovis , James Anthony Marcella
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C7/1018
摘要： A method and system for improving DRAM performance using burst refresh control reduces the overhead associated with refreshing DRAM in a computer system, making the memory more available to the devices that access it. Limiting the burst cycle to less than the entire DRAM array provides a lower latency than existing full DRAM burst techniques.
摘要翻译：使用突发刷新控制来提高DRAM性能的方法和系统减少了与计算机系统中的刷新DRAM相关联的开销，使得存储器对于访问它的设备更为可用。将突发周期限制为小于整个DRAM阵列提供比现有的全DRAM突发技术更低的延迟。

8. 发明授权

US06628662B1 Method and system for multilevel arbitration in a non-blocking crossbar switch 有权
标题翻译：非阻塞交叉开关中多级仲裁的方法和系统
公开(公告)号：US06628662B1
公开(公告)日：2003-09-30
申请号：US09450792
申请日：1999-11-29
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
IPC分类号： H04L12413
CPC分类号： H04L49/254 , H04L49/101 , H04L49/201 , H04L49/205
摘要： A method and system for arbitrating data transfers between devices connected via electronically isolated buses at a switch. In accordance with the method and system of the present invention, multiple arbitration controllers are interposed between devices and a switch to which the devices are connected, wherein each of the multiple arbitration controllers are effective to select a data transfer operation and detect collisions between said selected data transfer operations. The switch is enabled for any selected data transfer operations between which collisions are not detected. The switch is also enabled for only one of the selected data transfer operations between which collisions are detected. Any selected data transfer operations for which the switch is not enabled are deferred. The deferred data transfer operations are prioritized within the multiple arbitration controllers, such that for a subsequent selection of the deferred data transfer operations, the switch is enabled for the deferred data transfer operations.
摘要翻译：一种用于仲裁在交换机通过电子隔离总线连接的设备之间的数据传输的方法和系统。根据本发明的方法和系统，多个仲裁控制器被插在设备之间和设备连接的交换机之间，其中多个仲裁控制器中的每一个有效地选择数据传输操作并检测所选择的数据传输操作。对于未检测到碰撞的任何所选数据传输操作，该开关被使能。只有在检测到碰撞之间的所选数据传输操作中的一个时，该开关也被使能。任何未启用交换机的选定数据传输操作都会被延迟。延迟数据传输操作在多个仲裁控制器内被优先排列，使得对于延迟数据传输操作的后续选择，该交换机被启用用于延迟数据传输操作。

9. 发明授权

US06557069B1 Processor-memory bus architecture for supporting multiple processors 失效
标题翻译：用于支持多个处理器的处理器 - 内存总线架构
公开(公告)号：US06557069B1
公开(公告)日：2003-04-29
申请号：US09439189
申请日：1999-11-12
申请人： Robert Allen Drehmel , Kent Harold Haselhorst , Russell Dean Hoover , James Anthony Marcella , George Wayne Nation
发明人： Robert Allen Drehmel , Kent Harold Haselhorst , Russell Dean Hoover , James Anthony Marcella , George Wayne Nation
IPC分类号： G06F1300
CPC分类号： G06F15/16
摘要： An internal processor/memory bus contains an address portion for transmitting addresses and commands, having a series of hierarchical uni-directional links between processors and local repeaters (ARPs), and between the ARPs and a central repeater (ASW). A command propagates from a requesting device to its local ARP, to the ASW. From the ASW, the command is broadcast to all devices on the bus by transmitting to all ARPs or directly attached memory, and from the ARPs to the devices. Preferably, the ASW globally arbitrates the address bus, and all commands propagate at pre-defined clock cycles through the bus. Preferably, each device on the bus independently signals a response via a separate response link running directly to a global collector, which collects all responses and broadcasts a single system-wide response back to the devices. In the preferred embodiment, addresses/commands and data are transmitted on essentially separate paths having different topologies, and at different times, and are arbitrated separately. The data portion of the network comprises a set of bi-directional links from the processors to a local data switch unit (DSW). The local DSW is further linked directly to memory via bi-directional links. No address is transmitted with the data; rather, a tag is transmitted which identifies the original command.
摘要翻译：内部处理器/存储器总线包含用于发送地址和命令的地址部分，在处理器和本地中继器（ARP）之间以及ARP和中央中继器（ASW）之间具有一系列分层单向链路。命令从请求设备传播到其本地ARP，传送到ASW。从ASW，该命令通过传输到所有ARP或直接连接的内存，从ARP广播到总线上的所有设备。优选地，ASW全局仲裁地址总线，并且所有命令以预定义的时钟周期通过总线传播。优选地，总线上的每个设备独立地通过直接运行到全局收集器的单独响应链路来发送响应，该收集器收集所有响应并将单个系统范围响应广播到设备。在优选实施例中，地址/命令和数据在具有不同拓扑的基本上独立的路径上传输，并且在不同的时间被分开仲裁。网络的数据部分包括从处理器到本地数据交换单元（DSW）的一组双向链路。本地DSW通过双向链路进一步直接连接到存储器。没有地址与数据一起传输; 而是发送标识原始命令的标签。

10. 发明授权

US5748919A Shared bus non-sequential data ordering method and apparatus 失效
公开(公告)号：US5748919A
公开(公告)日：1998-05-05
申请号：US677775
申请日：1996-07-10
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
IPC分类号： G06F13/42 , G06F13/40 , G06F12/00 , G06F13/00
CPC分类号： G06F13/4018
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

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