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1. 发明授权

US06646949B1 Word line driver for dynamic random access memories 有权
标题翻译：用于动态随机存取存储器的字线驱动
公开(公告)号：US06646949B1
公开(公告)日：2003-11-11
申请号：US09537498
申请日：2000-03-29
申请人： Wayne F. Ellis , Louis L-C. Hsu , Jack A. Mandelman , William R. Tonti
发明人： Wayne F. Ellis , Louis L-C. Hsu , Jack A. Mandelman , William R. Tonti
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line for a row of memory elements of a dynamic random access memory. A first transistor is connected to a source of negative potential and to the word line for switching the word line to a source of negative potential in response to a decoder signal. A diode is additionally connected to the word line and to a selector signal. A second transistor applies a positive potential to the word line in response to a decoder signal. The word line is charged to a positive potential. The word line is reset to a substantially negative potential in two stages. In the first stage, conduction is through the diode to a ground connection which dissipates a majority of the charge of the word line. The remaining charge is dissipated during a second stage when the first transistor discharges the word line remaining charge through a source of negative potential.
摘要翻译：用于动态随机存取存储器的一行存储元件的字线。第一晶体管连接到负电位源和字线，用于响应于解码器信号将字线切换到负电位源。二极管另外连接到字线和选择器信号。第二晶体管响应于解码器信号向字线施加正电位。字线被充电到正电位。字线在两个阶段重置为基本上为负的电位。在第一阶段，传导通过二极管到接地连接，消耗字线的大部分电荷。当第一晶体管通过负电位源将字线剩余电荷放电时，剩余电荷在第二阶段消散。

2. 发明授权

US5260233A Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding 失效
标题翻译：半导体器件和晶片结构通过晶片接合具有平面埋入互连
公开(公告)号：US5260233A
公开(公告)日：1993-11-09
申请号：US973131
申请日：1992-11-06
申请人： Taqi N. Buti , Louis L-C. Hsu , Rajiv V. Joshi , Joseph F. Shepard
发明人： Taqi N. Buti , Louis L-C. Hsu , Rajiv V. Joshi , Joseph F. Shepard
IPC分类号： H01L21/3205 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/98 , H01L23/522 , H01L27/04 , H01L21/76
CPC分类号： H01L25/50 , H01L21/743 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L2924/0002 , Y10S148/012 , Y10S148/135 , Y10S438/977
摘要： A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate having an oxide layer thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

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