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1. 发明授权

US06693338B2 Power semiconductor device having RESURF layer 有权
标题翻译：具有RESURF层的功率半导体器件
公开(公告)号：US06693338B2
公开(公告)日：2004-02-17
申请号：US10163651
申请日：2002-06-07
申请人： Wataru Saitoh , Ichiro Omura , Masakazu Yamaguchi , Satoshi Aida , Syotaro Ono
发明人： Wataru Saitoh , Ichiro Omura , Masakazu Yamaguchi , Satoshi Aida , Syotaro Ono
IPC分类号： H01L2358
CPC分类号： H01L29/7811 , H01L21/26586 , H01L21/3247 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66712 , H01L29/7802 , H01L29/7816 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a drain layer, first and second drift layers, a RESURF layer, a drain electrode, a base layer, a source layer, a source electrode, and a gate electrode. The first drift layer is formed on the drain layer. The second drift layers and RESURF layers are formed on the first drift layer and periodically arranged in a direction perpendicular to the direction of depth. The RESURF layer forms a depletion layer in the second drift layer by a p-n junction including the second drift layer and RESURF layer. The impurity concentration in the first drift layer is different from that in the second drift layer. The drain electrode is electrically connected to the drain layer.
摘要翻译：半导体器件包括漏极层，第一和第二漂移层，RESURF层，漏极，基极层，源极层，源极和栅电极。第一漂移层形成在漏极层上。第二漂移层和RESURF层形成在第一漂移层上并且沿与深度方向垂直的方向周期性地布置。 RESURF层通过包括第二漂移层和RESURF层的p-n结在第二漂移层中形成耗尽层。第一漂移层中的杂质浓度不同于第二漂移层中的杂质浓度。漏电极与漏极层电连接。

2. 发明授权

US06700156B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US06700156B2
公开(公告)日：2004-03-02
申请号：US10321613
申请日：2002-12-18
申请人： Wataru Saitoh , Ichiro Omura , Satoshi Aida
发明人： Wataru Saitoh , Ichiro Omura , Satoshi Aida
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/42372 , H01L29/7395 , H01L29/7813
摘要： An insulated gate semiconductor device includes a first semiconductor layer of a first conductivity type. A plurality of second semiconductor layers of a second conductivity type selectively formed in a surface area of the first semiconductor layer. At least one third semiconductor layer of the first conductivity type is formed in a surface area of each of the second semiconductor layers. A fourth semiconductor layer is formed on a bottom of the first semiconductor layer. At least one fifth semiconductor layer of the second conductivity type is provided in the first semiconductor layer and connected to at least one of the plurality of second semiconductor layers. The fifth semiconductor layer has impurity concentration that is lower than that of the second semiconductor layers.
摘要翻译：绝缘栅半导体器件包括第一导电类型的第一半导体层。选择性地形成在第一半导体层的表面区域中的多个第二导电类型的第二半导体层。第一导电类型的至少一个第三半导体层形成在每个第二半导体层的表面区域中。在第一半导体层的底部形成第四半导体层。第二导电类型的至少一个第五半导体层被提供在第一半导体层中并连接到多个第二半导体层中的至少一个。第五半导体层的杂质浓度低于第二半导体层的杂质浓度。

3. 发明授权

US06919610B2 Power semiconductor device having RESURF layer 失效
标题翻译：具有RESURF层的功率半导体器件
公开(公告)号：US06919610B2
公开(公告)日：2005-07-19
申请号：US10714916
申请日：2003-11-18
申请人： Wataru Saitoh , Ichiro Omura
发明人： Wataru Saitoh , Ichiro Omura
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/78 , H01L23/58
CPC分类号： H01L29/7811 , H01L21/26586 , H01L21/3247 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66712 , H01L29/7802 , H01L29/7816 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a drain layer having a first conductivity type, a drift layer having the first conductivity type, which is formed on the drain layer and has an impurity concentration lower than that in the drain layer, and a RESURF layer having a second conductivity type and formed to extend from a surface of the drift layer into the drain layer, the RESURF layer forming a superjunction structure together with the drift layer and forming a depletion layer in the drift layer.
摘要翻译：一种半导体器件，包括具有第一导电类型的漏极层，具有第一导电类型的漂移层，其形成在漏极层上并且具有低于漏极层中的杂质浓度，以及具有第二导电性的RESURF层形成为从漂移层的表面延伸到漏极层，RESURF层与漂移层一起形成超结构结构，并在漂移层中形成耗尽层。

4. 发明申请

US20060017096A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060017096A1
公开(公告)日：2006-01-26
申请号：US10936601
申请日：2004-09-09
申请人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
发明人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
IPC分类号： H01L31/113
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/402 , H01L29/41741 , H01L29/7802
摘要： A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.
摘要翻译：公开了一种半导体器件，其包括形成为围绕器件有源区域的端子部分。端子部分包括形成在半导体层中的沟槽和填充在沟槽中的填充物。场板从形成在器件有源区域中的半导体元件的电极延伸到沟槽上方。

5. 发明授权

US07564107B2 Power semiconductor device including a terminal structure 有权
标题翻译：功率半导体器件包括端子结构
公开(公告)号：US07564107B2
公开(公告)日：2009-07-21
申请号：US10936601
申请日：2004-09-09
申请人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
发明人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/402 , H01L29/41741 , H01L29/7802
摘要： A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.
摘要翻译：公开了一种半导体器件，其包括形成为围绕器件有源区域的端子部分。端子部分包括形成在半导体层中的沟槽和填充在沟槽中的填充物。场板从形成在器件有源区域中的半导体元件的电极延伸到沟槽上方。

6. 发明授权

US06930352B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US06930352B2
公开(公告)日：2005-08-16
申请号：US10463613
申请日：2003-06-18
申请人： Wataru Saito , Ichiro Omura , Satoshi Aida
发明人： Wataru Saito , Ichiro Omura , Satoshi Aida
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/739 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/7397 , H01L29/7813
摘要： An insulated gate semiconductor device includes a control electrode having a trench type structure formed on the surface of a first semiconductor layer of a first conductivity type via a gate insulation film and disposed in a lattice shape, the control electrode having a plurality of first control electrode sections and a plurality of second control electrode sections which intersect with the plurality of first control electrode sections, respectively, and a plurality of fifth semiconductor layers of a second conductivity type which are provided on an interface of the first semiconductor layer in contact with the plurality of second control electrode sections, and connected to at least one of a plurality of second semiconductor layers of the second conductivity type, the fifth semiconductor layers having impurity concentration lower than that of the plurality of second semiconductor layers.
摘要翻译：一种绝缘栅半导体器件，包括：控制电极，具有通过栅极绝缘膜形成在第一导电类型的第一半导体层的表面上并且格栅形状的沟槽型结构，所述控制电极具有多个第一控制电极分别与多个第一控制电极部分相交的多个第二控制电极部分和多个第二导电类型的第五半导体层，其设置在第一半导体层的与多个第一控制电极部分接触的界面上的第二控制电极部分，并且连接到第二导电类型的多个第二半导体层中的至少一个，所述第五半导体层的杂质浓度低于多个第二半导体层的杂质浓度。

7. 发明授权

US06849880B1 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US06849880B1
公开(公告)日：2005-02-01
申请号：US10795325
申请日：2004-03-09
申请人： Wataru Saito , Ichiro Omura , Satoshi Aida
发明人： Wataru Saito , Ichiro Omura , Satoshi Aida
IPC分类号： H01L29/78 , H01L21/336 , H01L21/76 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/402 , H01L29/41775 , H01L29/42372 , H01L29/7813
摘要： A power semiconductor device includes second layers of a second conductivity type disposed in a first layer of a first conductivity type. The second layers extend in a depth direction and are arrayed at intervals. Third layers of the second conductivity type are disposed respectively in contact with the second layers. Fourth layers of the first conductivity type are respectively formed in surfaces of the third layers. A gate electrode faces, through a first insulating film, a channel region, which is each of portions of the third layers interposed between the fourth layers and the first layer. An additional electrode is disposed on each of the second layers through a second insulating film, and faces, through each of the second layers, the first main electrode. The additional electrode is electrically connected to the gate electrode.
摘要翻译：功率半导体器件包括设置在第一导电类型的第一层中的第二导电类型的第二层。第二层在深度方向上延伸并且以间隔排列。第二导电类型的第三层分别设置为与第二层接触。第一导电类型的第四层分别形成在第三层的表面中。栅电极通过第一绝缘膜面向通道区域，沟道区域是介于第四层和第一层之间的第三层的每个部分。附加电极通过第二绝缘膜设置在每个第二层上，并且通过每个第二层面向第一主电极。附加电极电连接到栅电极。

8. 发明申请

US20110042715A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110042715A1
公开(公告)日：2011-02-24
申请号：US12917614
申请日：2010-11-02
申请人： Masanori Tsukuda , Ichiro Omura
发明人： Masanori Tsukuda , Ichiro Omura
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0661 , H01L29/0696 , H01L29/0834 , H01L29/66348
摘要： A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.
摘要翻译：半导体器件包括半导体衬底; 设置在半导体衬底中的第一导电类型的第一基极区域; 所述第一导电类型的缓冲区域设置在所述第一基极区域的下表面上，并且具有高于所述第一基极区域的杂质浓度的杂质浓度; 设置在所述缓冲区域的下表面上的第二导电类型的发射极区域; 所述第二导电类型的第二基极区域选择性地设置在所述第一基极区域的上表面上; 所述第一导电类型的扩散区域选择性地设置在所述第二基极区域的上表面上; 控制电极; 第一主电极; 和第二主电极。缓冲区域和第一基底区域之间的结界面具有凹部和凸部。

9. 发明申请

US20090206365A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090206365A1
公开(公告)日：2009-08-20
申请号：US12368573
申请日：2009-02-10
申请人： Masanori Tsukuda , Ichiro Omura
发明人： Masanori Tsukuda , Ichiro Omura
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0661 , H01L29/0696 , H01L29/0834 , H01L29/66348
摘要： A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.
摘要翻译：半导体器件包括半导体衬底; 设置在半导体衬底中的第一导电类型的第一基极区域; 所述第一导电类型的缓冲区域设置在所述第一基极区域的下表面上，并且具有高于所述第一基极区域的杂质浓度的杂质浓度; 设置在缓冲区域的下表面上的第二导电类型的发射极区域; 所述第二导电类型的第二基极区域选择性地设置在所述第一基极区域的上表面上; 所述第一导电类型的扩散区域选择性地设置在所述第二基极区域的上表面上; 控制电极; 第一主电极; 和第二主电极。缓冲区域和第一基底区域之间的结界面具有凹部和凸部。

10. 发明授权

US07508015B2 Semiconductor device using a nitride semiconductor 有权
标题翻译：使用氮化物半导体的半导体装置
公开(公告)号：US07508015B2
公开(公告)日：2009-03-24
申请号：US11354148
申请日：2006-02-15
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L31/0328
CPC分类号： H01L29/432 , H01L29/1066 , H01L29/2003 , H01L29/402 , H01L29/4236 , H01L29/7786 , H01L29/7787
摘要： A semiconductor device includes: a first semiconductor layer represented by a composition formula AlxGa1-xN (0≦x≦1); a first conductivity type or non-doped second semiconductor layer represented by a composition formula AlyGa1-yN (0≦y≦1, x
摘要翻译：半导体器件包括：由组成式Al x Ga 1-x N（0≤x≤1）表示的第一半导体层; 由第一半导体层形成的由组成式AlyGa1-yN（0≤y≤1，x

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