专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060017096A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060017096A1
公开(公告)日：2006-01-26
申请号：US10936601
申请日：2004-09-09
申请人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
发明人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
IPC分类号： H01L31/113
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/402 , H01L29/41741 , H01L29/7802
摘要： A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.
摘要翻译：公开了一种半导体器件，其包括形成为围绕器件有源区域的端子部分。端子部分包括形成在半导体层中的沟槽和填充在沟槽中的填充物。场板从形成在器件有源区域中的半导体元件的电极延伸到沟槽上方。

2. 发明授权

US07564107B2 Power semiconductor device including a terminal structure 有权
标题翻译：功率半导体器件包括端子结构
公开(公告)号：US07564107B2
公开(公告)日：2009-07-21
申请号：US10936601
申请日：2004-09-09
申请人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
发明人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/402 , H01L29/41741 , H01L29/7802
摘要： A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.
摘要翻译：公开了一种半导体器件，其包括形成为围绕器件有源区域的端子部分。端子部分包括形成在半导体层中的沟槽和填充在沟槽中的填充物。场板从形成在器件有源区域中的半导体元件的电极延伸到沟槽上方。

3. 发明授权

US06930352B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US06930352B2
公开(公告)日：2005-08-16
申请号：US10463613
申请日：2003-06-18
申请人： Wataru Saito , Ichiro Omura , Satoshi Aida
发明人： Wataru Saito , Ichiro Omura , Satoshi Aida
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/739 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/7397 , H01L29/7813
摘要： An insulated gate semiconductor device includes a control electrode having a trench type structure formed on the surface of a first semiconductor layer of a first conductivity type via a gate insulation film and disposed in a lattice shape, the control electrode having a plurality of first control electrode sections and a plurality of second control electrode sections which intersect with the plurality of first control electrode sections, respectively, and a plurality of fifth semiconductor layers of a second conductivity type which are provided on an interface of the first semiconductor layer in contact with the plurality of second control electrode sections, and connected to at least one of a plurality of second semiconductor layers of the second conductivity type, the fifth semiconductor layers having impurity concentration lower than that of the plurality of second semiconductor layers.
摘要翻译：一种绝缘栅半导体器件，包括：控制电极，具有通过栅极绝缘膜形成在第一导电类型的第一半导体层的表面上并且格栅形状的沟槽型结构，所述控制电极具有多个第一控制电极分别与多个第一控制电极部分相交的多个第二控制电极部分和多个第二导电类型的第五半导体层，其设置在第一半导体层的与多个第一控制电极部分接触的界面上的第二控制电极部分，并且连接到第二导电类型的多个第二半导体层中的至少一个，所述第五半导体层的杂质浓度低于多个第二半导体层的杂质浓度。

4. 发明授权

US06849880B1 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US06849880B1
公开(公告)日：2005-02-01
申请号：US10795325
申请日：2004-03-09
申请人： Wataru Saito , Ichiro Omura , Satoshi Aida
发明人： Wataru Saito , Ichiro Omura , Satoshi Aida
IPC分类号： H01L29/78 , H01L21/336 , H01L21/76 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/402 , H01L29/41775 , H01L29/42372 , H01L29/7813
摘要： A power semiconductor device includes second layers of a second conductivity type disposed in a first layer of a first conductivity type. The second layers extend in a depth direction and are arrayed at intervals. Third layers of the second conductivity type are disposed respectively in contact with the second layers. Fourth layers of the first conductivity type are respectively formed in surfaces of the third layers. A gate electrode faces, through a first insulating film, a channel region, which is each of portions of the third layers interposed between the fourth layers and the first layer. An additional electrode is disposed on each of the second layers through a second insulating film, and faces, through each of the second layers, the first main electrode. The additional electrode is electrically connected to the gate electrode.
摘要翻译：功率半导体器件包括设置在第一导电类型的第一层中的第二导电类型的第二层。第二层在深度方向上延伸并且以间隔排列。第二导电类型的第三层分别设置为与第二层接触。第一导电类型的第四层分别形成在第三层的表面中。栅电极通过第一绝缘膜面向通道区域，沟道区域是介于第四层和第一层之间的第三层的每个部分。附加电极通过第二绝缘膜设置在每个第二层上，并且通过每个第二层面向第一主电极。附加电极电连接到栅电极。

5. 发明授权

US07317225B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US07317225B2
公开(公告)日：2008-01-08
申请号：US11551526
申请日：2006-10-20
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L29/76
CPC分类号： H01L29/66712 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/402 , H01L29/41741 , H01L29/7811
摘要： The power semiconductor device according to one embodiment of the present invention at least comprises: first pillar layers of the first conductive type and second pillar layers of a second conductive type which constitute a super-junction structure in a device section and which are arranged alternately in a horizontal direction, each of the first and second pillar layers having a column-shaped sectional structure; third pillar layers of the first conductive type and fourth pillar layers of the second conductive type which are adjacent to the super-junction structure of the device section to constitute another super-junction structure thinner in a vertical direction than the super-junction structure of the device section in a device termination section and which are arranged alternately in a horizontal direction, each of the third and fourth pillar layers having a column-shaped sectional structure; an outermost pillar layer which is stacked on one of the third or fourth pillar layers in the super-junction structure of the device termination section nearest to the device section to be additionally formed to an outermost portion of the super-junction structure of the device section nearest to the device termination section and which has an impurity concentration less than that of each of the first and second pillar layers; a high resistance layer of the first conductive type which is formed on the third pillar layers and the fourth pillar layers and has a resistance value higher than that of each of the first and second pillar layers.
摘要翻译：根据本发明的一个实施例的功率半导体器件至少包括：第一导电类型的第一柱层和第二导电类型的第二柱层，其在器件部分中构成超结结构，并且交替布置在水平方向，第一和第二柱层中的每一个具有柱状截面结构; 第二导电类型的第一导电类型和第四柱层的第三柱层与器件部分的超结结构相邻以构成在垂直方向上比第二导体类型的超结结构更薄的超结结构装置部分，其在水平方向上交替布置，每个第三和第四柱层都具有柱状截面结构; 最外层柱层层叠在最靠近器件部分的器件端接部分的超结结构中的第三或第四柱层之一上，以附加地形成在器件部分的超结结构的最外部分最靠近器件终止部分，其杂质浓度小于第一和第二柱层的杂质浓度; 所述第一导电类型的高电阻层形成在所述第三柱层和所述第四柱层上，并且具有高于所述第一和第二柱层中的每一个的电阻值。

6. 发明授权

US07238576B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07238576B2
公开(公告)日：2007-07-03
申请号：US10403122
申请日：2003-04-01
申请人： Masakazu Yamaguchi , Ichiro Omura , Wataru Saito , Takashi Shinohe , Hiromichi Ohashi
发明人： Masakazu Yamaguchi , Ichiro Omura , Wataru Saito , Takashi Shinohe , Hiromichi Ohashi
IPC分类号： H01L21/336
CPC分类号： H01L29/7803 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/66712 , H01L29/7722 , H01L29/7802 , H01L29/7805 , H01L29/7811 , H01L29/7813 , H01L29/7824
摘要： A semiconductor device comprises a drain layer of first conductivity type, drift layers of first and second conductivity types on the drain layer, an insulating film between the drift layers and contacting the drift layers, a first base layer of second conductivity type on a surface of the drift layer of first conductivity type, a source layer of first conductivity type selectively provided on a surface of the first base layer of second conductivity type, a gate insulating film on the first base layer of second conductivity type between the source layer and the drift layer, a gate electrode on the gate insulating film, a second base layer of second conductivity type on a surface of the drift layer, a first main electrode on the drain layer, and a second main electrode on the source layer, the first base layer and the second base layer.
摘要翻译：半导体器件包括第一导电类型的漏极层，漏极层上的第一和第二导电类型的漂移层，漂移层之间的绝缘膜和与漂移层接触的第二导电类型的第一基底层，第一导电类型的漂移层，选择性地设置在第二导电类型的第一基极层的表面上的第一导电类型的源极层，在源极层和漂移体之间的第二导电类型的第一基极层上的栅极绝缘膜栅极绝缘膜上的栅电极，漂移层的表面上的第二导电类型的第二基极层，漏极层上的第一主电极和源极层上的第二主电极，第一基极层和第二基层。

7. 发明授权

US07157748B2 Nitride-based semiconductor device 失效
标题翻译：氮化物半导体器件
公开(公告)号：US07157748B2
公开(公告)日：2007-01-02
申请号：US11014866
申请日：2004-12-20
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L31/00
CPC分类号： H01L29/7787 , H01L29/2003
摘要： A nitride-based semiconductor device includes a first semiconductor layer consisting essentially of a nitride-based semiconductor, and a second semiconductor layer disposed on the first semiconductor layer and consisting essentially of a non-doped or first conductivity type nitride-based semiconductor. The first and second semiconductor layers forms a hetero-interface. A gate electrode is disposed on the second semiconductor layer. First and second trenches are formed in a surface of the second semiconductor layer at positions sandwiching the gate electrode. Third and fourth semiconductor layers of the first conductivity type are respectively formed in surfaces of the first and second trenches and each consist essentially of a diffusion layer having a resistivity lower than the first and second semiconductor layers. Source and drain electrodes are electrically connected to the third and fourth semiconductor layers, respectively.
摘要翻译：氮化物基半导体器件包括基本上由氮化物基半导体组成的第一半导体层和设置在第一半导体层上并基本上由非掺杂或第一导电型氮化物基半导体构成的第二半导体层。第一和第二半导体层形成异质界面。栅电极设置在第二半导体层上。第一和第二沟槽在夹着栅电极的位置处形成在第二半导体层的表面中。第一导电类型的第三和第四半导体层分别形成在第一和第二沟槽的表面中，并且每个半导体层基本上由电阻率低于第一和第二半导体层的扩散层组成。源电极和漏电极分别电连接到第三和第四半导体层。

8. 发明申请

US20060284248A1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060284248A1
公开(公告)日：2006-12-21
申请号：US11453997
申请日：2006-06-16
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712
摘要： First semiconductor pillar layers of a first conduction type and second semiconductor pillar layers of a second conduction type are arranged on a first semiconductor layer of the first conduction type laterally, periodically and alternately at a first period to forma first pillar layer. Third semiconductor pillar layers of the first conduction type and fourth semiconductor pillar layers of the second conduction type are arranged on the first pillar layer laterally, periodically and alternately at a second period smaller than the first period to form a second pillar layer. A semiconductor base layer of the second conduction type is formed on a surface of the fourth semiconductor pillar layer. A semiconductor diffused layer of the first conduction type is formed on a surface of the semiconductor base layer.
摘要翻译：第一导电类型的第一半导体柱层和第二导电类型的第二半导体柱层被布置在第一导电类型的第一半导体层上，以第一周期方式，周期性地交替地布置以形成第一柱层。第二导电类型的第一导电类型的第三半导体柱层和第二导电类型的第四半导体柱层在第一柱层上以比第一周期小的周期性地交替布置在第一柱层上，以形成第二柱层。在第四半导体柱层的表面上形成第二导电类型的半导体基底层。在半导体基底层的表面上形成第一导电类型的半导体扩散层。

9. 发明申请

US20060131644A1 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US20060131644A1
公开(公告)日：2006-06-22
申请号：US11117342
申请日：2005-04-29
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L31/113
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0878 , H01L29/7397 , H01L29/872
摘要： A power semiconductor device includes second semiconductor layers of a first conductivity type and third semiconductor layers of a second conductivity type alternately disposed on a first semiconductor layer of the first conductivity type. The device further includes fourth semiconductor layers of the second conductivity type disposed in contact with upper portions of the third semiconductor layers between the second semiconductor layers, and fifth semiconductor layers of the first conductivity type formed in surfaces of the fourth semiconductor layers. The first semiconductor layer is lower in impurity concentration of the first conductivity type than each second semiconductor layer. The third semiconductor layer includes a fundamental portion and an impurity-amount-larger portion formed locally in a depth direction and higher in impurity amount than the fundamental portion. The impurity amount is defined by a total amount of impurities of the second conductivity type over a cross section in a lateral direction.
摘要翻译：功率半导体器件包括交替设置在第一导电类型的第一半导体层上的第一导电类型的第二半导体层和第二导电类型的第三半导体层。该器件还包括第二导电类型的第四半导体层，与第二半导体层之间的第三半导体层的上部接触，以及形成在第四半导体层的表面中的第一导电类型的第五半导体层。第一半导体层的第一导电类型的杂质浓度比每个第二半导体层低。第三半导体层包括基本部分和在深度方向上局部形成的杂质量较大部分，并且杂质量高于基本部分。杂质量由横向横截面上的第二导电类型的杂质的总量限定。

10. 发明授权

US07049658B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US07049658B2
公开(公告)日：2006-05-23
申请号：US10602596
申请日：2003-06-25
申请人： Wataru Saito , Ichiro Omura , Tsuneo Ogura
发明人： Wataru Saito , Ichiro Omura , Tsuneo Ogura
IPC分类号： H01L29/94
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0653 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a power semiconductor device, including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type which are alternately and laterally arranged on the first semiconductor layer and, a fourth semiconductor layer of the second conductivity type selectively formed in the surface regions of the second and third semiconductor layers, a fifth semiconductor layer of the first conductivity type selectively formed in the surface region of the fourth semiconductor layer, and a control electrode formed on the surfaces of the second, fourth and fifth semiconductor layers, in which a layer thickness ratio A is given by the expression: 0
摘要翻译：公开了一种功率半导体器件，包括第一导电类型的第一半导体层，第一导电类型的第二半导体层和第二导电类型的第三半导体层，其交替地和横向地布置在第一半导体层上，选择性地形成在第二和第三半导体层的表面区域中的第二导电类型的第四半导体层，选择性地形成在第四半导体层的表面区域中的第一导电类型的第五半导体层和形成在第二半导体层上的控制电极第二半导体层，第四半导体层和第五半导体层的表面，其中层厚度比A由以下表达式给出：<？in-line-formula description =“In-line Formulas”end =“lead”？> 0 其中t是第一半导体层的厚度，d是第二次 d半导体层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式