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1. 发明授权

US6136659A Production process for a capacitor electrode formed of a platinum metal 失效
标题翻译：由铂金属形成的电容器电极的制造方法
公开(公告)号：US6136659A
公开(公告)日：2000-10-24
申请号：US47850
申请日：1998-03-25
申请人： Gunther Schindler , Walter Hartner , Volker Weinrich , Carlos Mazure-Espejo
发明人： Gunther Schindler , Walter Hartner , Volker Weinrich , Carlos Mazure-Espejo
IPC分类号： H01L27/108 , H01L21/02 , H01L21/3213 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L21/20
CPC分类号： H01L28/65 , H01L21/32137
摘要： A production process for a capacitor electrode formed of a platinum metal includes producing a conductive electrode body on a substrate having a silicon-containing surface for the capacitor electrode. Platinum is deposited over the full surface, the platinum is silicized in a temperature step outside the electrode body and the platinum silicide is removed. The advantage of the invention is the avoidance of an etching process for metallic platinum.
摘要翻译：由铂金属形成的电容器电极的制造方法包括在具有用于电容器电极的含硅表面的基板上制造导电电极体。铂在整个表面上沉积，铂在电极体外部的温度阶段被硅化，除去铂硅化物。本发明的优点是避免金属铂的蚀刻工艺。

2. 发明授权

US6097050A Memory configuration with self-aligning non-integrated capacitor configuration 失效
标题翻译：具有自对准非集成电容配置的存储器配置
公开(公告)号：US6097050A
公开(公告)日：2000-08-01
申请号：US282041
申请日：1999-03-30
申请人： Walter Hartner , Gunther Schindler , Carlos Mazure-Espejo
发明人： Walter Hartner , Gunther Schindler , Carlos Mazure-Espejo
IPC分类号： H01L25/18 , H01L21/60 , H01L25/00 , H01L25/04 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/72
CPC分类号： H01L27/11502 , H01L24/81 , H01L2224/10135 , H01L2224/10165 , H01L2224/16237 , H01L2224/81139 , H01L2224/8114 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01041 , H01L2924/01056 , H01L2924/01073 , H01L2924/01082 , H01L2924/19041 , H01L2924/19043
摘要： A memory configuration with a self-aligning non-integrated capacitor configuration includes a capacitor configuration and a transistor configuration which can be joined together in a self-aligning manner in such a way that each first contact of a transistor of the transistor configuration is connected to a respective second contact of a memory capacitor of the capacitor configuration. In order to align the two configurations, the second contacts are constructed in a protruding manner, and when joining takes place they engage in a structure including elevations.
摘要翻译：具有自对准非集成电容器配置的存储器配置包括电容器配置和晶体管配置，其可以以自对准方式连接在一起，使得晶体管配置的晶体管的每个第一接触连接到电容器配置的存储电容器的相应的第二接触。为了对准这两种结构，第二触头以突出的方式构造，并且当接合发生时，它们接合包括高度的结构。

3. 发明授权

US6043529A Semiconductor configuration with a protected barrier for a stacked cell 失效
标题翻译：具有用于堆叠单元的受保护屏障的半导体构造
公开(公告)号：US6043529A
公开(公告)日：2000-03-28
申请号：US282099
申请日：1999-03-30
申请人： Walter Hartner , Gunther Schindler , Carlos Mazure-Espejo
发明人： Walter Hartner , Gunther Schindler , Carlos Mazure-Espejo
IPC分类号： H01L21/02 , H01L21/8246 , H01L29/78
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： The invention relates to a semiconductor configuration for integrated circuits, in which a stacked cell has a contact hole filled with a plug in an insulating layer, a capacitor having a lower electrode, which faces the plug, a paraelectric or ferroelectric dielectric and an upper electrode being provided on the contact hole. A barrier layer is situated between the plug and the lower electrode and is surrounded by a silicon nitride collar, which reliably prevents oxidation of the barrier layer.
摘要翻译：本发明涉及一种用于集成电路的半导体结构，其中堆叠单元具有填充有绝缘层的插塞的接触孔，具有面向插塞的下电极的电容器，顺电或铁电电介质和上电极设置在接触孔上。阻挡层位于插塞和下电极之间，并且被氮化硅套环围绕，可靠地防止阻挡层的氧化。

4. 发明授权

US06197633B1 Method for the production of an integrated semiconductor memory configuration 有权
标题翻译：用于生产集成半导体存储器配置的方法
公开(公告)号：US06197633B1
公开(公告)日：2001-03-06
申请号：US09281822
申请日：1999-03-30
申请人： Günther Schindler , Walter Hartner , Carlos Mazure-Espejo
发明人： Günther Schindler , Walter Hartner , Carlos Mazure-Espejo
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for producing a memory configuration that comprises a multiplicity of memory cells, and has storage capacitors whose first electrodes are configured in plate form in a parallel manner one above the other. These electrodes are in electrical contact with selection transistors of the memory cell through contact plugs having different lengths. The first electrodes preferably extend beyond the cell area of one memory cell.
摘要翻译：一种用于产生包括多个存储单元的存储器配置的方法，并且具有其第一电极以彼此并列的方式配置为板形的存储电容器。这些电极通过具有不同长度的接触插塞与存储器单元的选择晶体管电接触。优选地，第一电极延伸超过一个存储单元的单元区域。

5. 发明授权

US06316802B1 Easy to manufacture integrated semiconductor memory configuration with platinum electrodes 失效
标题翻译：易于制造的集成半导体存储器配置采用铂电极
公开(公告)号：US06316802B1
公开(公告)日：2001-11-13
申请号：US09282091
申请日：1999-03-30
申请人： Günther Schindler , Walter Hartner , Frank Hintermaier , Carlos Mazure-Espejo , Rainer Bruchhaus , Wolfgang Hönlein , Manfred Engelhardt
发明人： Günther Schindler , Walter Hartner , Frank Hintermaier , Carlos Mazure-Espejo , Rainer Bruchhaus , Wolfgang Hönlein , Manfred Engelhardt
IPC分类号： H01L27108
CPC分类号： H01L27/11502
摘要： The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.
摘要翻译：集成半导体存储器配置具有集成了选择晶体管和存储电容器的半导体本体。存储电容器具有在两个电极之间配置的电介质层。至少上电极以分层的方式构成，铂层位于电介质层上，而较厚的贱金属层位于铂层之上。

6. 发明授权

US06168988A Method for producing barrier-free semiconductor memory configurations 有权
标题翻译：无障碍半导体存储器配置的制造方法
公开(公告)号：US06168988A
公开(公告)日：2001-01-02
申请号：US09281691
申请日：1999-03-30
申请人： G{umlaut over (u)}nther Schindler , Walter Hartner , Frank Hintermaier , Carlos Mazure-Espejo
发明人： G{umlaut over (u)}nther Schindler , Walter Hartner , Frank Hintermaier , Carlos Mazure-Espejo
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/10808 , H01L27/10852 , H01L27/11517 , H01L28/55
摘要： A method for producing an integrated semiconductor memory configuration, in particular uses ferroelectric materials as storage dielectrics. A conductive connection between a first electrode of a storage capacitor and a selection transistor is produced only after deposition of the storage dielectric.
摘要翻译：一种用于制造集成半导体存储器配置的方法，特别地使用铁电材料作为存储电介质。存储电容器的第一电极和选择晶体管之间的导电连接仅在沉积存储电介质之后产生。

7. 发明授权

US06414300B1 Circuit with a sensor and non-volatile memory having a ferroelectric dielectric capacitor 有权
标题翻译：具有传感器的电路和具有铁电介质电容器的非易失性存储器
公开(公告)号：US06414300B1
公开(公告)日：2002-07-02
申请号：US09674628
申请日：2000-02-05
申请人： Carlos Mazure-Espejo , Christoph Zeller
发明人： Carlos Mazure-Espejo , Christoph Zeller
IPC分类号： H01L3100
CPC分类号： G11C11/2259 , G11C11/221 , H01L27/14609
摘要： A circuit includes a sensor delivering a charge, a capacitor non-volatilely storing the charge, and a read and reset circuit reading out the stored charge. The capacitor has further connection terminals connected to the read and reset circuit and in parallel with the sensor terminals, and a ferroelectric storage dielectric intermittently connected to the sensor. The sensor can be a photodiode, a phototransistor, a Hall sensor, or a thermoelement. A switch can be connected between one of the further terminals and one of the sensor terminals. Preferably, the switch is a transistor and a drive circuit drives it. The sensor and the capacitor are formed in a semiconductor body. During a storage procedure, time periods during which the switch is on are coordinated with the sensor and/or capacitor to keep an electrical field present between the further terminals below a maximum value at which the ferroelectric dielectric saturates.
摘要翻译：电路包括传送电荷的传感器，非易失性地存储电荷的电容器以及读出存储的电荷的读取和复位电路。电容器具有连接到读取和复位电路并与传感器端子并联的另外的连接端子，以及间断地连接到传感器的铁电存储介质。传感器可以是光电二极管，光电晶体管，霍尔传感器或热电偶。开关可以连接在其他端子之一和传感器端子之一之间。优选地，开关是晶体管，驱动电路驱动它。传感器和电容器形成在半导体本体中。在存储过程期间，开关导通的时间周期与传感器和/或电容器协调，以使得在另外的端子之间存在低于铁电介质饱和的最大值的电场。

8. 发明授权

US06627934B1 Integrated semiconductor memory configuration with a buried plate electrode and method for its fabrication 失效
标题翻译：具有掩埋板电极的集成半导体存储器配置及其制造方法
公开(公告)号：US06627934B1
公开(公告)日：2003-09-30
申请号：US09281696
申请日：1999-03-30
申请人： Günther Schindler , Carlos Mazure-Espejo
发明人： Günther Schindler , Carlos Mazure-Espejo
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , H01L27/10805 , H01L27/10829
摘要： A semiconductor memory configuration has a plurality of selection transistors. Each selection transistor is connected to a first electrode of a storage capacitor. A second electrode of the storage capacitor is connected to a common plate. The common plate is provided below the selection transistors in a semiconductor body. A method of fabricating a semiconductor memory configuration is also provided.
摘要翻译：半导体存储器配置具有多个选择晶体管。每个选择晶体管连接到存储电容器的第一电极。存储电容器的第二电极连接到公共板。公共板设置在半导体本体中的选择晶体管的下方。还提供了制造半导体存储器配置的方法。

9. 发明授权

US06605505B2 Process for producing an integrated semiconductor memory configuration 有权
标题翻译：用于制造集成半导体存储器配置的方法
公开(公告)号：US06605505B2
公开(公告)日：2003-08-12
申请号：US09883011
申请日：2001-06-15
申请人： Frank Hintermaier , Carlos Mazure-Espejo
发明人： Frank Hintermaier , Carlos Mazure-Espejo
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/10808 , H01L27/10852 , H01L27/11517 , H01L28/55
摘要： A process for producing an integrated semiconductor memory configuration, in particular one suited to the use of ferroelectric materials as storage dielectrics, in which a conductive connection between one electrode of a storage capacitor and a selection transistor is not produced until after the storage dielectric has been deposited; and a semiconductor memory configuration produced using the production process.
摘要翻译：一种用于制造集成半导体存储器配置的方法，特别是适合于使用铁电材料作为存储电介质的方法，其中在存储电容器的一个电极和选择晶体管的一个电极之间的导电连接直到存储电介质已经被存放以及使用该制造工艺制造的半导体存储器配置。

10. 发明授权

US6100187A Method of producing a barrier layer in a semiconductor body 失效
标题翻译：在半导体本体中制造阻挡层的方法
公开(公告)号：US6100187A
公开(公告)日：2000-08-08
申请号：US106237
申请日：1998-06-29
申请人： Frank Hintermaier , Carlos Mazure-Espejo
发明人： Frank Hintermaier , Carlos Mazure-Espejo
IPC分类号： H01L27/108 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L21/44
CPC分类号： H01L28/60 , H01L21/76838
摘要： A barrier layer is formed on the contact plug of the semiconductor body. The barrier layer prevents oxidation of the contact plug. The barrier layer is produced by chemically reacting a prestructured metallic transition material with one or more reaction partners.
摘要翻译：在半导体本体的接触插塞上形成阻挡层。阻挡层防止接触塞的氧化。通过使预结构的金属过渡材料与一个或多个反应配对物化学反应来制备阻挡层。

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