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1. 发明申请

US20090250784A1 Structure and method for elimination of process-related defects in poly/metal plate capacitors 审中-公开
标题翻译：消除多金属/金属板电容器工艺相关缺陷的结构和方法
公开(公告)号：US20090250784A1
公开(公告)日：2009-10-08
申请号：US12156503
申请日：2008-06-02
申请人： Walter B. Meinel , Henry Surtihadi , Philipp Steinmann , David J. Hannaman
发明人： Walter B. Meinel , Henry Surtihadi , Philipp Steinmann , David J. Hannaman
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L21/84 , H01L27/1203 , H01L28/60
摘要： An integrated circuit includes silicon layer (2) supported by a bottom oxide layer (3), a shallow trench oxide (4) in the shallow trench (30), and a polycrystalline silicon layer (5) on the shallow trench oxide. A deep trench oxide (25) extending from the shallow trench oxide to the bottom oxide layer electrically isolates a section (2A) of the silicon layer to prevent a silicon cone defect (22) on the silicon layer (2) from causing short-circuiting of the polycrystalline silicon layer (5) to a non-isolated section of the silicon layer. The polycrystalline silicon layer (5) can form a bottom plate of a poly/metal capacitor (20) and can also form a poly interconnect conductor (5A).
摘要翻译：集成电路包括由底部氧化物层（3）支撑的硅层（2），浅沟槽（30）中的浅沟槽氧化物（4）和浅沟槽氧化物上的多晶硅层（5）。从浅沟槽氧化物延伸到底部氧化物层的深沟槽氧化物（25）将硅层的部分（2A）电隔离以防止硅层（2）上的硅锥缺陷（22）引起短路的多晶硅层（5）到硅层的非隔离部分。多晶硅层（5）可以形成多晶硅/金属电容器（20）的底板，并且还可以形成多晶硅互连导体（5A）。

2. 发明授权

US07403094B2 Thin film resistor and dummy fill structure and method to improve stability and reduce self-heating 有权
标题翻译：薄膜电阻和虚拟填充结构和方法，以提高稳定性和减少自热
公开(公告)号：US07403094B2
公开(公告)日：2008-07-22
申请号：US11103203
申请日：2005-04-11
申请人： Eric W. Beach , Walter B. Meinel , Philipp Steinmann
发明人： Eric W. Beach , Walter B. Meinel , Philipp Steinmann
IPC分类号： H01C1/012
CPC分类号： H01L27/016 , H01L23/5228 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit thin film resistor structure includes a first dielectric layer (18A) disposed on a semiconductor layer (16), a first dummy fill layer (9A) disposed on the first dielectric layer (18B), a second dielectric layer (18C) disposed on the first dummy fill layer (9A), the second dielectric layer (18B) having a first planar surface (18-3), a first thin film resistor (2) disposed on the first planar surface (18-3) over the first dummy fill layer (9A). A first metal interconnect layer (22A,B) includes a first portion (22A) contacting a first head portion of the thin film resistor (2). A third dielectric layer (21) is disposed on the thin film resistor (2) and the first metal interconnect layer (22A,B). Preferably, the first thin film resistor (2) is symmetrically aligned with the first dummy fill layer (9A). In the described embodiments, the first dummy fill layer is composed of metal (integrated circuit metallization).
摘要翻译：一种集成电路薄膜电阻器结构，包括设置在半导体层（16）上的第一介电层（18A），设置在第一介电层（18B）上的第一虚拟填充层（9A）），第二介电层 18A），所述第二电介质层（18B）具有第一平坦表面（18-3），第一薄膜电阻器（2）设置在所述第一平坦表面（18）上，所述第一平坦表面 3）在第一虚拟填充层（9A）上。第一金属互连层（22A，B）包括接触薄膜电阻器（2）的第一头部的第一部分（22A）。第三电介质层（21）设置在薄膜电阻器（2）和第一金属互连层（22A，B）上。优选地，第一薄膜电阻器（2）与第一虚拟填充层（9A）对称地对准。在所描述的实施例中，第一虚拟填充层由金属（集成电路金属化）组成。

3. 发明申请

US20120138800A1 ON-CHIP CALIBRATION SYSTEM AND METHOD FOR INFRARED SENSOR 审中-公开
标题翻译：用于红外传感器的片上校准系统和方法
公开(公告)号：US20120138800A1
公开(公告)日：2012-06-07
申请号：US13396408
申请日：2012-02-14
申请人： Walter B. Meinel , Kalin V. Lazarov
发明人： Walter B. Meinel , Kalin V. Lazarov
IPC分类号： G01J5/22 , H01L21/66
CPC分类号： G01J5/12 , G01J5/22 , G01J2005/0048
摘要： A radiation sensor includes an integrated circuit radiation sensor chip (1A) including first (7) and second (8) thermopile junctions connected in series to form a thermopile (7,8) within a dielectric stack (3). The first thermopile junction (7) is insulated from a substrate (2) of the chip. A resistive heater (6) in the dielectric stack for heating the first thermopile junction is coupled to a calibration circuit (67) for calibrating responsivity of the thermopile (7,8). The calibration circuit causes a current flow in the heater and multiplies the current by a resulting voltage across the heater to determine power dissipation. A resulting thermoelectric voltage (Vout) of the thermopile (7,8) is divided by the power to provide the responsivity of the sensor.
摘要翻译：辐射传感器包括集成电路辐射传感器芯片（1A），其包括串联连接的第一（7）和第二（8）热电堆接头，以在电介质叠层（3）内形成热电堆（7,8）。第一热电堆结（7）与芯片的基片（2）绝缘。用于加热第一热电堆结的电介质堆叠中的电阻加热器（6）耦合到用于校准热电堆（7,8）的响应度的校准电路（67）。校准电路导致加热器中的电流流动，并将电流乘以加热器两端的所得电压，以确定功率耗散。热电堆（7,8）的所得热电电压（Vout）除以功率以提供传感器的响应度。

4. 发明授权

US06828856B2 Amplifier gain boost circuitry and method 有权
公开(公告)号：US06828856B2
公开(公告)日：2004-12-07
申请号：US10698661
申请日：2003-10-31
申请人： Stephen J. Sanchez , Vadim V. Ivanov , Walter B. Meinel
发明人： Stephen J. Sanchez , Vadim V. Ivanov , Walter B. Meinel
IPC分类号： H03F345
CPC分类号： H03F3/45192 , H03F2203/45028 , H03F2203/45301 , H03F2203/45302 , H03F2203/45682
摘要： A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.

5. 发明授权

US06819148B2 CMOS comparator output stage and method 有权
标题翻译： CMOS比较器输出级和方法
公开(公告)号：US06819148B2
公开(公告)日：2004-11-16
申请号：US10201816
申请日：2002-07-23
申请人： Vadim V. Ivanov , Shoubao Yan , Walter B. Meinel
发明人： Vadim V. Ivanov , Shoubao Yan , Walter B. Meinel
IPC分类号： H03K300
CPC分类号： H03K17/08122 , H03K19/0013 , H03K2217/0036
摘要： A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal, (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).
摘要翻译：包括P沟道上拉晶体管（MP）和N沟道下拉晶体管（MN）的CMOS电路包括产生第一延迟信号的第一反馈电路（6），在栅极的栅极上产生（V7）降低晶体管（MN），以在上拉晶体管（MP）完全关断之后，将下拉晶体管（MN）导通第一预定量的时间，以防止任何直通电流流过拉（MP）和下拉晶体管（MN）和第二反馈电路（4），在上拉晶体管（MP）的栅极上产生第二延迟信号（V5），以接通上拉电阻晶体管（MP）在下拉晶体管（MN）完全关断之后的第二预定量的时间，以防止任何直通电流流过上拉晶体管（MP）和下拉晶体管（ MN）。

6. 发明授权

US5592124A Integrated photodiode/transimpedance amplifier 失效
标题翻译：集成光电二极管/跨阻放大器
公开(公告)号：US5592124A
公开(公告)日：1997-01-07
申请号：US494413
申请日：1995-06-26
申请人： Edward Mullins , Rodney T. Burt , Walter B. Meinel , R. Mark Stitt, II
发明人： Edward Mullins , Rodney T. Burt , Walter B. Meinel , R. Mark Stitt, II
IPC分类号： H03F1/08 , H03F3/08
CPC分类号： H03F1/08 , H03F3/08
摘要： An integrated circuit photodetector includes a transimpedance amplifier including a differential amplifier stage with PNP emitter-coupled transistors and a PNP input transistor which are biased only by base currents of the emitter-coupled transistors, to achieve low input bias current. Low noise operation is achieved by bypass capacitors coupled between the bases and emitters of the input transistors, respectively. A constant current source supplies a current which develops a small pedestal voltage across a resistor to bias the non-inverting input of the transimpedance amplifier so as to avoid nonlinear amplification of low level light signals. A positively biased N-type guard tub surrounds the photodetector, which is formed in a junction-isolated N region on a P substrate, to collect electrons generated in the substrate by deep-penetrating IR light to prevent them from causing amplification errors. In one embodiment, a feedback network includes a resistor connected between the output of a buffer driven by the transimpedance amplifier and an inverting input thereof, and a capacitor connected between the output and inverting input of the transimpedance amplifier to provide low noise, fast settling operation.
摘要翻译：集成电路光电检测器包括跨阻抗放大器，其包括具有PNP发射极耦合晶体管的差分放大器级和仅由发射极耦合晶体管的基极电流偏置的PNP输入晶体管，以实现低输入偏置电流。分别通过耦合在输入晶体管的基极和发射极之间的旁路电容来实现低噪声操作。恒流源提供电流，该电流在电阻器两端产生小的基座电压，以偏置跨阻放大器的非反相输入，以避免低电平光信号的非线性放大。正偏置N型保护桶围绕形成在P基板上的结隔离N区域中的光电检测器，以通过深穿透IR光收集在衬底中产生的电子，以防止它们引起放大误差。在一个实施例中，反馈网络包括连接在由跨阻抗放大器驱动的缓冲器的输出与其反相输入之间的电阻器，以及连接在跨阻放大器的输出和反相输入端之间以提供低噪声，快速稳定操作。

7. 发明授权

US5353001A Hybrid integrated circuit planar transformer 失效
标题翻译：混合集成电路平面变压器
公开(公告)号：US5353001A
公开(公告)日：1994-10-04
申请号：US969508
申请日：1992-10-30
申请人： Walter B. Meinel , R. Mark Stitt, II
发明人： Walter B. Meinel , R. Mark Stitt, II
IPC分类号： H01F19/00 , H01F17/00 , H01F19/04 , H01F27/255 , H01F27/28 , H05K1/16 , H01F27/26 , H01F27/30
CPC分类号： H01F19/04 , H01F17/0006 , H05K1/165 , H05K2201/086 , H05K2201/09063 , Y10T29/4902
摘要： A planar transformer includes a multilayer printed circuit board having a plurality of spiral windings formed by metalization on various surfaces of the printed circuit board. A ferrite core assembly includes first and second core sections disposed on opposite sides of the printed circuit board and completely confining the conductors of the spiral windings. Each core section includes a thin, flat plate. The two flat plates are integral with or abut thin post sections that are thick enough to allow the printed circuit board to be accommodated between the first and second core sections. In one embodiment of the invention, the planar transformer is incorporated on the printed circuit board with other circuitry to form a low noise battery charger which is encapsulated in a male power connector.
摘要翻译：平面变压器包括多层印刷电路板，其具有通过在印刷电路板的各个表面上的金属化形成的多个螺旋绕组。铁氧体磁芯组件包括设置在印刷电路板的相对侧上的第一和第二磁芯部分，并完全限制螺旋绕组的导体。每个芯部分包括一个薄的平板。两个平板与足够厚的薄柱部分是一体的或邻接的，使得印刷电路板能够容纳在第一和第二芯部之间。在本发明的一个实施例中，平面变压器与其他电路结合在印刷电路板上，以形成封装在公电源连接器中的低噪声电池充电器。

8. 发明授权

US4777465A Square toroid transformer for hybrid integrated circuit 失效
标题翻译：用于混合集成电路的方形环形变压器
公开(公告)号：US4777465A
公开(公告)日：1988-10-11
申请号：US882071
申请日：1986-07-02
申请人： Walter B. Meinel
发明人： Walter B. Meinel
IPC分类号： H01F19/06 , H01F17/00 , H01F17/06 , H01F27/28 , H01F30/16 , H01G4/012 , H01G4/38 , H01L23/64 , H01L25/16 , H05K1/03 , H05K1/16 , H01F15/02 , H01F27/30
CPC分类号： H01G4/012 , H01F17/0033 , H01F17/062 , H01F27/2804 , H01F30/16 , H01G4/38 , H01L23/642 , H01L25/165 , H05K1/162 , H01F2027/2814 , H01L2224/49175 , H01L24/49 , H01L2924/00014 , H01L2924/01014 , H01L2924/01019 , H01L2924/01057 , H01L2924/01063 , H01L2924/01068 , H01L2924/01079 , H01L2924/14 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H05K1/0306 , H05K2201/09236 , H05K2201/10946 , Y10T29/4902 , Y10T29/49073
摘要： A square toroid transformer is assembled on a ceramic hybrid integrated circuit substrate. The primary and secondary windings of the transformer are provided on opposite arms of a square toroid ferrite core by providing first and second groups of spaced, parallel metal conductors on the surface of the ceramic substrate and adherent thereto, and an insulative layer over the first and second groups of conductors, leaving their respective end portions exposed. The square toroid ferrite core, coated with dielectric material, is attached to the insulative layer. Wire bonds in planes perpendicular to the longitudinal axes of the opposite arms each are wire bonded, respectively, to an inner end of one of the metal conductors and an outer end of an adjacent one. A large number of turns for both the primary winding and the secondary winding are achieved, resulting in high primary and secondary winding and inductances, while maintaining a uniform separation and high breakdown voltage between the primary and secondary wirings.
摘要翻译：方形环形变压器组装在陶瓷混合集成电路基板上。变压器的初级和次级绕组通过在陶瓷衬底的表面上提供第一和第二组相互平行的间隔开的金属导体并与之粘合在一起，在方形环形铁氧体磁芯的相对臂上设置绝缘层，第二组导体，使它们各自的端部露出。将绝缘材料涂覆的方形环形铁氧体磁心附着在绝缘层上。垂直于相对臂的纵轴的平面中的线接合部分别分别连接到金属导体中的一个的内端和相邻的一个的外端。实现了初级绕组和次级绕组的大量匝数，从而导致高次级绕组和电感，同时保持初级和次级绕组之间的均匀分离和高的击穿电压。

9. 发明授权

US08607631B2 Heated air mass WCSP package and method for accelerometer 有权
标题翻译：加热空气质量WCSP封装及加速度计方法
公开(公告)号：US08607631B2
公开(公告)日：2013-12-17
申请号：US13066746
申请日：2011-04-22
申请人： Walter B. Meinel , Kalin V. Lazarov
发明人： Walter B. Meinel , Kalin V. Lazarov
IPC分类号： G01P15/00 , G01P15/08
CPC分类号： G01P15/008 , G01P5/18
摘要： An inertial sensor (16) includes a differential thermocouple (13) including first (4A) and second (4B) metal traces, a poly trace (6) with a first end connected to a first end of the first metal trace to form a first (−) thermocouple junction and a second end connected to a first end of the second metal trace to form a second (+) thermocouple junction. A gas mass (10) located symmetrically with respect to the thermocouple junctions is heated by a heater (8). Acceleration or tilting of the sensor shifts the relative location of the gas mass relative to the thermocouple junctions, causing differential heating thereof and generation of a corresponding thermocouple output signal.
摘要翻译：惯性传感器（16）包括包括第一（4A）和第二（4B）金属迹线的差分热电偶（13），多迹线（6），其第一端连接到第一金属迹线的第一端，以形成第一（ - ）热电偶结，并且第二端连接到第二金属迹线的第一端以形成第二（+）热电偶结。通过加热器（8）加热位于热电偶接头对称的气体（10）。传感器的加速或倾斜使气体质量体的相对位置相对于热电偶接头移位，导致其不同的加热并产生相应的热电偶输出信号。

10. 发明授权

US08115272B2 Silicon dioxide cantilever support and method for silicon etched structures 有权
标题翻译：二氧化硅悬臂支撑和硅蚀刻结构的方法
公开(公告)号：US08115272B2
公开(公告)日：2012-02-14
申请号：US13208098
申请日：2011-08-11
申请人： Walter B. Meinel , Kalin V. Lazarov , Brian E. Goodlin
发明人： Walter B. Meinel , Kalin V. Lazarov , Brian E. Goodlin
IPC分类号： H01L21/70
CPC分类号： H01L28/40 , H01L21/764 , H01L27/08 , H01L28/10 , H01L28/20 , H01L31/101
摘要： An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.
摘要翻译：一种装置包括其中具有空腔（4）的半导体层（2）。在半导体层上形成介电层（3）。多个蚀刻剂开口（24）延伸穿过介电层，用于通过蚀刻剂以蚀刻空腔。 SiO 2柱（25）从空腔的底部延伸以接合并支撑在腔上延伸的介电层的一部分。在一个实施例中，电介质层上的覆盖层（34）覆盖蚀刻剂开口。

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