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1. 发明授权

US08445913B2 Metal-insulator-metal (MIM) device and method of formation thereof 有权
公开(公告)号：US08445913B2
公开(公告)日：2013-05-21
申请号：US11980213
申请日：2007-10-30
申请人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
发明人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
IPC分类号： H01L29/12
CPC分类号： H01L28/40 , H01G4/10 , H01G13/00 , H01L27/101 , H01L28/57 , Y10T29/435
摘要： In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.

2. 发明申请

US20090109598A1 Metal-insulator-metal (MIM) device and method of formation thereof 有权
标题翻译：金属绝缘体金属（MIM）器件及其形成方法
公开(公告)号：US20090109598A1
公开(公告)日：2009-04-30
申请号：US11980213
申请日：2007-10-30
申请人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
发明人： Steven Avanzino , Tzu-Ning Fang , Swaroop Kaza , Dongxiang Liao , Wai Lo , Christie Marrian , Sameer Haddad
IPC分类号： H01G4/002 , H01G7/00
CPC分类号： H01L28/40 , H01G4/10 , H01G13/00 , H01L27/101 , H01L28/57 , Y10T29/435
摘要： In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.
摘要翻译：在制造金属 - 绝缘体 - 金属（MIM）器件的方法中，首先提供第一电极。在第一电极上设置氧化物层，在氧化物层上设置保护层。提供通过保护层的开口以暴露氧化物层的一部分，氧化层的暴露部分下方的第一电极的一部分被氧化。提供与氧化物层的暴露部分接触的第二电极。在替代实施例中，可以消除初始提供的氧化物层，并且可以在开口中提供绝缘材料的间隔物。

3. 发明授权

US07916529B2 Pin diode device and architecture 有权
标题翻译： pin二极管器件和架构
公开(公告)号：US07916529B2
公开(公告)日：2011-03-29
申请号：US12370932
申请日：2009-02-13
申请人： Wai Lo , Christie Marrian , Tzu-Ning Fang , Sameer Haddad
发明人： Wai Lo , Christie Marrian , Tzu-Ning Fang , Sameer Haddad
IPC分类号： G11C11/36
CPC分类号： H01L27/1021 , G11C5/04 , G11C11/36 , H01L27/24 , H01L29/868
摘要： A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.
摘要翻译：提供采用一个或多个半导体PIN二极管的存储架构。存储器采用包括掩埋位/字线和PIN二极管的衬底。 PIN二极管包括非本征半导体区域，位/字线的一部分和位于非固有区域和位/字线部分之间的本征半导体区域。

4. 发明申请

US20100208517A1 PIN DIODE DEVICE AND ARCHITECTURE 有权
标题翻译： PIN二极管器件和架构
公开(公告)号：US20100208517A1
公开(公告)日：2010-08-19
申请号：US12370932
申请日：2009-02-13
申请人： Wai Lo , Christie Marrian , Tzu-Ning Fang , Sameer Haddad
发明人： Wai Lo , Christie Marrian , Tzu-Ning Fang , Sameer Haddad
IPC分类号： G11C11/36 , H01L29/868 , H01L21/425 , G11C7/00
CPC分类号： H01L27/1021 , G11C5/04 , G11C11/36 , H01L27/24 , H01L29/868
摘要： A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.
摘要翻译：提供采用一个或多个半导体PIN二极管的存储架构。存储器采用包括掩埋位/字线和PIN二极管的衬底。 PIN二极管包括非本征半导体区域，位/字线的一部分和位于非固有区域和位/字线部分之间的本征半导体区域。

5. 发明授权

US09274410B2 Method and system for automated generation of masks for spacer formation from a desired final wafer pattern 有权
标题翻译：用于从期望的最终晶片图案自动生成用于间隔物形成的掩模的方法和系统
公开(公告)号：US09274410B2
公开(公告)日：2016-03-01
申请号：US12701391
申请日：2010-02-05
申请人： Wai Lo , Todd Lukanc , Christie Marrian
发明人： Wai Lo , Todd Lukanc , Christie Marrian
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/14 , G03F1/70
摘要： Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.
摘要翻译：公开了用于产生用于间隔物形成的掩模的方法和系统。作为所公开的方法的一部分，访问预定义的最终晶片图案，识别与预定的最终晶片图案中的特征相关的区域，并且基于用于在晶片上形成间隔物的所识别的区域形成模板掩模。随后，形成用于去除间隔物的部分以形成对应于预定的最终晶片图案的晶片图案的掩模。

6. 发明申请

US20110195348A1 METHOD AND SYSTEM FOR AUTOMATED GENERATION OF MASKS FOR SPACER FORMATION FROM A DESIRED FINAL WAFER PATTERN 有权
标题翻译：用于自动生成用于从预期的最终波形图形形成的掩模的方法和系统
公开(公告)号：US20110195348A1
公开(公告)日：2011-08-11
申请号：US12701391
申请日：2010-02-05
申请人： Wai Lo , Todd Lukanc , Christie Marrian
发明人： Wai Lo , Todd Lukanc , Christie Marrian
IPC分类号： G03F1/00 , B05C11/00
CPC分类号： G03F1/14 , G03F1/70
摘要： Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.
摘要翻译：公开了用于产生用于间隔物形成的掩模的方法和系统。作为所公开的方法的一部分，访问预定义的最终晶片图案，识别与预定的最终晶片图案中的特征相关的区域，并且基于用于在晶片上形成间隔物的所识别的区域形成模板掩模。随后，形成用于去除间隔物的部分以形成对应于预定的最终晶片图案的晶片图案的掩模。

7. 发明授权

US07829936B2 Split charge storage node inner spacer process 有权
标题翻译：分离电荷存储节点内隔离过程
公开(公告)号：US07829936B2
公开(公告)日：2010-11-09
申请号：US11873822
申请日：2007-10-17
申请人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R. K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
发明人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R. K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
IPC分类号： H01L21/331
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42344
摘要： Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
摘要翻译：提供了在半导体衬底上形成包含两个分开的次光刻电荷存储节点的存储单元的方法。这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。通过去除第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。此外，通过去除电荷存储层的暴露部分，同时保留由两个分割子光刻第一多晶硅栅极保护的电荷存储层的部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个拆分次光刻电荷存储节点。

8. 发明授权

US07807580B2 Triple poly-si replacement scheme for memory devices 有权
标题翻译：存储器件的三重多晶硅替代方案
公开(公告)号：US07807580B2
公开(公告)日：2010-10-05
申请号：US11742003
申请日：2007-04-30
申请人： Chungho Lee , Huaqiang Wu , Wai Lo , Hiroyuki Kinoshita
发明人： Chungho Lee , Huaqiang Wu , Wai Lo , Hiroyuki Kinoshita
IPC分类号： H01L21/302
CPC分类号： H01L27/11573 , H01L21/28282
摘要： A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery regions; removing the second poly and second top oxide in the periphery region; and forming a third poly on the semiconductor substrate in both the core and periphery regions.
摘要翻译：提供了替换存储器件的存储元件周围的顶部氧化物的方法。该方法可以包括在核心区域中去除核心的第一多核和第一顶部氧化物，而不去除半导体衬底上的外围区域中的周边第一多晶硅; 在所述芯区域中的存储元件周围和所述周边区域的所述外围第一聚四氟乙烯上形成第二顶部氧化物; 在所述芯和外围区域中在所述半导体衬底上形成第二聚合物; 去除所述周边区域中的所述第二聚合物和第二顶部氧化物; 以及在所述芯和外围区域中在所述半导体衬底上形成第三聚合物。

9. 发明申请

US20080150090A1 DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL 审中-公开
标题翻译：使用Si1-xGex作为材料的具有控制门型材和长度的金属浇注过程
公开(公告)号：US20080150090A1
公开(公告)日：2008-06-26
申请号：US12021728
申请日：2008-01-29
申请人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
发明人： Hong Lin , Wai Lo , Sey-Shing Sun , Richard Carter
IPC分类号： H01L29/40
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28123 , H01L21/32134 , H01L21/32137
摘要： A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySi1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
摘要翻译：一种在晶片中形成金属栅极的方法。多晶硅1-x x Ge x S和多晶硅用于形成锥形槽。栅极氧化物，多晶硅1-x x Ge x，并且多晶硅沉积在晶片上。形成抗蚀剂图案。去除多晶硅的一部分，多晶硅1-x N x N x N和栅极氧化物以提供锥形轮廓。去除抗蚀剂; 沉积电介质衬垫，然后去除电介质衬垫的至少一部分，从而暴露多晶硅并使电介质衬垫与多晶硅接触，多晶硅1-x Ge x 和/或栅极氧化物。沉积电介质，一部分被去除，从而暴露多晶硅。从电介质衬垫的内部去除多晶硅，多晶硅1 x x Ge x x和栅极氧化物，从而留下锥形栅极沟槽。然后将金属沉积在凹槽中。

10. 发明授权

US07259462B1 Interconnect dielectric tuning 有权
标题翻译：互连电介质调谐
公开(公告)号：US07259462B1
公开(公告)日：2007-08-21
申请号：US11419548
申请日：2006-05-22
申请人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
发明人： Wai Lo , Hong Lin , Shiqun Gu , Wilbur G. Catabay , Zhihai Wang , Wei-Jen Hsia
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.
摘要翻译：对形成集成电路的方法的改进。形成蚀刻停止层以覆盖集成电路的前端处理层。形成支撑结构，其被布置为支撑集成电路的各个级别上的导电互连。基本上去除了在制造互连期间形成的蚀刻停止层上方的所有非导电层。

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