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1. 发明申请

US20140043892A1 SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE RESISTANCE MEMORY AND OPERATING METHOD 有权
标题翻译：具有可变电阻记忆和操作方法的半导体存储器件
公开(公告)号：US20140043892A1
公开(公告)日：2014-02-13
申请号：US13954161
申请日：2013-07-30
申请人： WONSEOK LEE , SEONGHYUN JEON , YOUNGKUG MOON , DONG HWI KIM
发明人： WONSEOK LEE , SEONGHYUN JEON , YOUNGKUG MOON , DONG HWI KIM
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1695
摘要： A semiconductor memory device includes a memory cell array of nonvolatile memory cells having a variable resistance element, and a conductor line array capable of generating a compensation magnetic field for the nonvolatile memory cells. A current driver selectively supplies current to conductive lines, a magnetic field sensor senses an applied external magnetic field and generates external magnetic field information, and a controller controls generation of the compensation magnetic field in response to the external magnetic field information.
摘要翻译：半导体存储器件包括具有可变电阻元件的非易失性存储单元的存储单元阵列和能够产生用于非易失性存储单元的补偿磁场的导线阵列。电流驱动器选择性地向导线提供电流，磁场传感器感测施加的外部磁场并产生外部磁场信息，并且控制器响应于外部磁场信息控制补偿磁场的产生。

2. 发明申请

US20140016397A1 NONVOLATILE MEMORY DEVICE AND WRITE METHOD THEREOF 审中-公开
标题翻译：非易失性存储器件及其写入方法
公开(公告)号：US20140016397A1
公开(公告)日：2014-01-16
申请号：US13939324
申请日：2013-07-11
申请人： WONSEOK LEE , SEONGHYUN JEON , DONG HWI KIM
发明人： WONSEOK LEE , SEONGHYUN JEON , DONG HWI KIM
IPC分类号： G11C13/00 , G11C7/10
CPC分类号： G11C13/0069 , G11C7/10 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C16/10 , G11C16/3431 , G11C16/349 , G11C2013/0076 , G11C2213/79
摘要： A nonvolatile memory device includes a memory cell array including a plurality of memory cells, and a data comparison write unit connected with the memory cell array and configured to support a comparison write operation. The nonvolatile memory device further includes control logic configured to selectively execute the comparison write operation based on a comparison between an access number of the memory cell array and a reference number.
摘要翻译：非易失性存储器件包括包括多个存储器单元的存储单元阵列和与存储单元阵列连接并被配置为支持比较写入操作的数据比较写入单元。非易失性存储器件还包括控制逻辑，配置为基于存储单元阵列的访问号与参考号之间的比较选择性地执行比较写入操作。

3. 发明申请

US20140032890A1 STORAGE DEVICE COMPRISING VARIABLE RESISTANCE MEMORY AND RELATED METHOD OF OPERATION 有权
标题翻译：包含可变电阻记忆体的存储装置及其相关操作方法
公开(公告)号：US20140032890A1
公开(公告)日：2014-01-30
申请号：US13951493
申请日：2013-07-26
申请人： WONSEOK LEE , SEONGHYUN JEON , Dong-Hwi KIM
发明人： WONSEOK LEE , SEONGHYUN JEON , Dong-Hwi KIM
IPC分类号： G06F9/44
CPC分类号： G06F9/4401 , G11C7/20 , G11C11/161 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C13/004 , G11C29/028 , G11C2029/0407 , G11C2029/4402
摘要： A storage device includes a nonvolatile memory device including a variable resistance memory, and a controller configured to control the nonvolatile memory device. At a booting operation, the controller stores booting information in the variable resistance memory of the nonvolatile memory device. At a rebooting operation, the controller selectively performs a warm boot operation using the booting information stored in the variable resistance memory, based on a comparison result between a booting setting condition associated with the booting operation and a rebooting condition associated with the rebooting operation.
摘要翻译：存储装置包括包括可变电阻存储器的非易失性存储器件，以及被配置为控制非易失性存储器件的控制器。在启动操作时，控制器将引导信息存储在非易失性存储器件的可变电阻存储器中。在重新启动操作时，控制器基于与引导操作相关联的引导设置条件与与重新启动操作相关联的重新启动条件之间的比较结果，选择性地使用存储在可变电阻存储器中的引导信息进行热启动操作。

4. 发明申请

US20140146621A1 NONVOLATILE MEMORY AND METHOD OF OPERATING NONVOLATILE MEMORY 有权
标题翻译：非易失性存储器和操作非易失性存储器的方法
公开(公告)号：US20140146621A1
公开(公告)日：2014-05-29
申请号：US14082210
申请日：2013-11-18
申请人： CHANKYUNG KIM , SANGBO LEE , SEONGHYUN JEON
发明人： CHANKYUNG KIM , SANGBO LEE , SEONGHYUN JEON
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C7/109 , G11C7/222 , G11C8/12 , G11C11/1653 , G11C11/1673 , G11C11/1675
摘要： A nonvolatile memory includes multiple banks, control logic and multiple read and write (RW) circuits. Each bank includes multiple memory cells. The control logic includes multiple storage units corresponding to the banks, respectively, and configured to output write enable signals and read enable signals to respective banks based on mode information stored in respective storage units. The RW circuits are connected to the banks, respectively, and are configured to independently enable or disable write and read operations of the respective banks in response to the write enable signals and the read enable signals of the respective banks. In an initial state after the mode information is stored in the respective storage units, the control logic activates the write enable signals and the read enable signals of the respective banks regardless of the mode information stored in the respective storage units.
摘要翻译：非易失性存储器包括多个存储体，控制逻辑和多个读写（RW）电路。每个存储体包括多个存储单元。控制逻辑分别包括对应于存储体的多个存储单元，并且被配置为基于存储在各个存储单元中的模式信息，将写使能信号和使能信号读取到各个存储体。 RW电路分别连接到存储体，并且被配置为响应于写入使能信号和各个存储体的读取使能信号独立地使能或禁止各个存储体的写入和读取操作。在模式信息被存储在各个存储单元中之后的初始状态下，无论存储在各个存储单元中的模式信息如何，控制逻辑激活各个存储体的写使能信号和读使能信号。

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