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1. 发明申请

US20150003281A1 SCALABLE MULTI-LAYER 2D-MESH ROUTERS 有权
标题翻译：可扩展的多层2D网路路由器
公开(公告)号：US20150003281A1
公开(公告)日：2015-01-01
申请号：US13927523
申请日：2013-06-26
申请人： William C. Hasenplaugh , Tryggve Fossum , Judson S. Leonard
发明人： William C. Hasenplaugh , Tryggve Fossum , Judson S. Leonard
IPC分类号： H04L12/933 , H04L12/24 , H04L12/733
CPC分类号： H04L49/15 , H04L41/12 , H04L45/12 , H04L45/122 , H04L49/101 , H04L49/25
摘要： Architectures, apparatus and systems employing scalable multi-layer 2D-mesh routers. A 2D router mesh comprises bi-direction pairs of linked paths coupled between pairs of IO interfaces and configured in a plurality of rows and columns forming a 2D mesh. Router nodes are located at the intersections of the rows and columns, and are configured to forward data units between IO inputs and outputs coupled to the mesh at its edges through use of shortest path routes defined by agents at the IO interfaces. Multiple instances of the 2D meshes may be employed to support bandwidth scaling of the router architecture. One implementation of a multi-layer 2D mesh is built using a standard tile that is tessellated to form a 2D array of standard tiles, with each 2D mesh layer offset and overlaid relative to the other 2D mesh layers. IO interfaces are then coupled to the multi-layer 2D mesh via muxes/demuxes and/or crossbar interconnects.
摘要翻译：采用可扩展多层二维网状路由器的架构，设备和系统。 2D路由器网格包括耦合在IO对接口之间的双向对链接路径，并且被配置成形成2D网格的多个行和列。路由器节点位于行和列的交点处，并且被配置为通过使用由IO接口上的代理定义的最短路径路由来在IO输入和耦合到其边缘的网格的输出之间转发数据单元。可以采用2D网格的多个实例来支持路由器架构的带宽缩放。使用被镶嵌的标准瓦片来构建多层2D网格的一个实施方式，以形成标准瓦片的2D阵列，其中每个2D网格层相对于其他2D网格层偏移并重叠。然后，IO接口通过多路复用/解复用和/或交叉连接互连到多层2D网格。

2. 发明申请

US20130173893A1 HARDWARE COMPILATION AND/OR TRANSLATION WITH FAULT DETECTION AND ROLL BACK FUNCTIONALITY 有权
公开(公告)号：US20130173893A1
公开(公告)日：2013-07-04
申请号：US13341812
申请日：2011-12-30
申请人： Nicholas Cheng Hwa Chee , Tryggve Fossum , William C. Hasenplaugh
发明人： Nicholas Cheng Hwa Chee , Tryggve Fossum , William C. Hasenplaugh
IPC分类号： G06F9/318 , G06F9/312
CPC分类号： G06F8/44 , G06F9/3001 , G06F9/30087 , G06F9/30174 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/462 , G06F11/0751
摘要： Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states.

3. 发明授权

US08893094B2 Hardware compilation and/or translation with fault detection and roll back functionality 有权
标题翻译：具有故障检测和回滚功能的硬件编译和/或翻译
公开(公告)号：US08893094B2
公开(公告)日：2014-11-18
申请号：US13341812
申请日：2011-12-30
申请人： Nicholas Cheng Hwa Chee , Tryggve Fossum , William C. Hasenplaugh
发明人： Nicholas Cheng Hwa Chee , Tryggve Fossum , William C. Hasenplaugh
IPC分类号： G06F9/45 , G06F7/38 , G06F11/00 , G06F9/38 , G06F9/46 , G06F11/07
CPC分类号： G06F8/44 , G06F9/3001 , G06F9/30087 , G06F9/30174 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/462 , G06F11/0751
摘要： Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states.
摘要翻译：公开了具有故障检测和回滚功能的硬件编译和/或翻译。编译和/或翻译逻辑接收以一种语言编码的程序，并且将该程序编码成包括指令的第二语言，以支持未被编码为程序的原始语言编码的处理器特征。在一个实施例中，执行单元执行包括执行第一操作的操作检查指令的第二语言的指令并记录用于比较的第一操作结果，以及执行第二操作和故障检测操作的操作测试指令通过比较第二操作结果与记录的第一操作结果。在一些实施例中，执行单元执行第二语言的指令，包括提交指令以记录映射到架构寄存器的寄存器的执行检查点状态，以及回滚指令，将映射到架构寄存器的寄存器恢复到先前记录的执行检查点状态。

4. 发明申请

US20120246407A1 METHOD AND SYSTEM TO IMPROVE UNALIGNED CACHE MEMORY ACCESSES 审中-公开
标题翻译：改进高速缓存存储器访问的方法和系统
公开(公告)号：US20120246407A1
公开(公告)日：2012-09-27
申请号：US13052468
申请日：2011-03-21
申请人： WILLIAM C. HASENPLAUGH , Tryggve Fossum
发明人： WILLIAM C. HASENPLAUGH , Tryggve Fossum
IPC分类号： G06F12/08
CPC分类号： G06F12/0846
摘要： A method and system to improve unaligned cache memory accesses. In one embodiment of the invention, a processing unit has logic to facilitate access of at least two cache memory lines of a cache memory in a single read operation. By doing so, it avoids additional read operations or cycles to read the required data that is cached in more than one cache memory line. Embodiments of the invention facilitate the streaming of unaligned vector loads that does not require substantially more power than streaming aligned vector loads. For example, in one embodiment of the invention, the streaming of unaligned vector loads consumes less than two times the power requirements of streaming aligned vector loads.
摘要翻译：一种改善未对齐缓存存储器访问的方法和系统。在本发明的一个实施例中，处理单元具有便于在单次读取操作中访问高速缓冲存储器的至少两个高速缓存存储器线路的逻辑。通过这样做，它避免了额外的读取操作或循环来读取缓存在多个缓存存储器行中的所需数据。本发明的实施例有助于不需要比流对齐矢量负载大得多的功率的未对齐矢量负载的流。例如，在本发明的一个实施例中，未对齐矢量负载的流量消耗小于流对齐矢量负载的功率需求的两倍。

5. 发明申请

US20140189413A1 DISTRIBUTED POWER MANAGEMENT FOR MULTI-CORE PROCESSORS 有权
标题翻译：多核处理器的分布式电源管理
公开(公告)号：US20140189413A1
公开(公告)日：2014-07-03
申请号：US13732289
申请日：2012-12-31
申请人： William C. Hasenplaugh , Tryggve Fossum
发明人： William C. Hasenplaugh , Tryggve Fossum
IPC分类号： G06F1/28
CPC分类号： G06F1/3206 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G06F9/3885 , G06F9/5094 , Y02D10/152 , Y02D10/22
摘要： A system and method for performing distributed power control in a processor comprising an array of cores enables each core to regulate power at least partially independently. Global power management settings are made accessible to all cores and communication between cores propagates power consumption information between nearest neighbors in the array. Each core attempts to best regulate its own power consumption in accordance with global power consumption information and/or specific instructions from a global power manager. In this manner local opportunistic load balancing may be achieved in a scalable manner suitable for a large array of cores.
摘要翻译：用于在包括核心阵列的处理器中执行分布式功率控制的系统和方法使得每个核心能够至少部分地独立地调节功率。所有核心都可以访问全局电源管理设置，并且内核之间的通信会传播阵列中最近邻居之间的功耗信息。每个核心都尝试根据全球功耗信息和/或来自全球电源管理员的特定指令来最佳地调节其自身的功耗。以这种方式，可以以适合于大型核心阵列的可扩展方式来实现本地机会性负载平衡。

6. 发明授权

US08190863B2 Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction 有权
标题翻译：通过资源分配和限制的异构芯片多处理器的装置和方法
公开(公告)号：US08190863B2
公开(公告)日：2012-05-29
申请号：US10884359
申请日：2004-07-02
申请人： Tryggve Fossum , George Chrysos , Todd A. Dutton
发明人： Tryggve Fossum , George Chrysos , Todd A. Dutton
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F13/00 , G06F13/28 , G06F1/00
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/3287 , G06F9/30181 , G06F9/3802 , G06F9/3869 , G06F9/5061 , G06F9/5094 , Y02D10/171 , Y02D10/22
摘要： A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.
摘要翻译：一种通过资源限制的异构芯片多处理器（CMP）的方法和装置。在一个实施例中，该方法包括访问资源利用寄存器以识别资源利用策略。一旦被访问，处理器控制器确保处理器核心以资源利用策略指定的方式利用共享资源。在一个实施例中，CMP内的每个处理器核心包括指令发布节流阀资源利用寄存器，指令提取节流阀资源利用寄存器以及在最小和最大利用水平内限制其对共享资源的利用的类似方式。在一个实施例中，资源限制提供了将电流和功率资源分配给可由硬件或软件控制的CMP的处理器核心的灵活方式。描述和要求保护其他实施例。

7. 发明授权

US07380169B2 Converting merge buffer system-kill errors to process-kill errors 有权
标题翻译：将合并缓冲区系统杀死错误转换为进程杀死错误
公开(公告)号：US07380169B2
公开(公告)日：2008-05-27
申请号：US10948904
申请日：2004-09-24
申请人： Tryggve Fossum , Yaron Shragai , Ugonna Echeruo , Shubhendu S. Mukherjee
发明人： Tryggve Fossum , Yaron Shragai , Ugonna Echeruo , Shubhendu S. Mukherjee
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F9/3824 , G06F9/3861 , G06F11/0715 , G06F11/1016 , G06F11/1032
摘要： An apparatus includes a buffer that collects store instruction information associated with one or more processes. The collected store instruction information includes data and addresses where the data are to be stored. The apparatus also includes a buffer control that drains the buffer of store instructions associated with a first process before it collects store instructions associated with a second process.
摘要翻译：一种装置包括收集与一个或多个处理相关联的存储指令信息的缓冲器。收集的存储指令信息包括要存储数据的数据和地址。该装置还包括缓冲器控制，其在收集与第二进程相关联的存储指令之前，将与第一进程相关联的存储指令的缓冲器排出。

8. 发明授权

US07370231B2 Method of handling errors 有权
标题翻译：处理错误的方法
公开(公告)号：US07370231B2
公开(公告)日：2008-05-06
申请号：US11012979
申请日：2004-12-14
申请人： Tryggve Fossum , Yaron Shragai , Shubhendu S. Mukherjee
发明人： Tryggve Fossum , Yaron Shragai , Shubhendu S. Mukherjee
IPC分类号： G06F11/00
CPC分类号： G06F11/0721 , G06F11/0793
摘要： An error handling routine of a processor, executing in response to a first detected unrecoverable error (DUE) of the processor, responding to an indication that a second DUE has occurred by evaluating the effect of the second DUE on the correctness of the error handling routine.
摘要翻译：处理器的错误处理程序，响应于处理器的第一检测到的不可恢复错误（DUE）执行，响应于通过评估第二DUE对错误处理例程的正确性的影响而发生第二DUE的指示。

9. 发明授权

US5829051A Apparatus and method for intelligent multiple-probe cache allocation 失效
标题翻译：智能多探头缓存分配的装置和方法
公开(公告)号：US5829051A
公开(公告)日：1998-10-27
申请号：US223069
申请日：1994-04-04
申请人： Simon C. Steely, Jr. , Richard B. Gillett, Jr. , Tryggve Fossum
发明人： Simon C. Steely, Jr. , Richard B. Gillett, Jr. , Tryggve Fossum
IPC分类号： G06F12/08 , G06F9/26
CPC分类号： G06F12/0864
摘要： An apparatus for allocating data to and retrieving data from a cache includes a memory subsystem coupled between a processor and a memory to provide quick access of memory data to the processor. The memory subsystem includes a cache memory. The address provided to the memory subsystem is divided into a cache index and a tag, and the cache index is hashed to provide a plurality of alternative addresses for accessing the cache. During a cache read, each of the alternative addresses are selected to search for the data responsive to an indicator of the validity of the data at the locations. The selection of the alternative address may be done through a mask having a number of bits corresponding to the number of alternative addresses. Each bit indicates whether the alternative address at that location should be used during the access of the cache in search of the data. Alternatively, a memory device which has more entries than the cache has blocks may be used to store the select value of the best alternative address to use to locate the data. Data is allocated to each alternative address based upon a modified least recently used technique wherein a quantum number and modula counter are used to time stamp the data.
摘要翻译：一种用于向高速缓存提供数据并从其中检索数据的装置包括耦合在处理器和存储器之间的存储器子系统，以便将存储器数据快速地存取到处理器。存储器子系统包括高速缓冲存储器。提供给存储器子系统的地址被划分为高速缓存索引和标签，并且高速缓存索引被散列以提供用于访问高速缓存的多个替代地址。在缓存读取期间，选择每个备选地址以响应于在该位置处的数据的有效性的指示符来搜索数据。替代地址的选择可以通过具有对应于替代地址的数量的位数的掩码来完成。每个位指示在缓存访问期间是否应该使用该位置处的替代地址来搜索数据。或者，具有比高速缓存具有更多条目的存储器装置可以用于存储用于定位数据的最佳替代地址的选择值。基于修改的最近最少使用的技术将数据分配给每个备选地址，其中使用量子数和模数计数器来对数据进行时间戳。

10. 发明授权

US5113521A Method and apparatus for handling faults of vector instructions causing memory management exceptions 失效
标题翻译：用于处理导致内存管理异常的向量指令故障的方法和装置
公开(公告)号：US5113521A
公开(公告)日：1992-05-12
申请号：US638149
申请日：1991-01-09
申请人： Francis X. McKeen , Tryggve Fossum , Dileep P. Bhandarkar , Cheryl A. Wiecek
发明人： Francis X. McKeen , Tryggve Fossum , Dileep P. Bhandarkar , Cheryl A. Wiecek
IPC分类号： G06F9/46
CPC分类号： G06F9/462
摘要： A data processing system handles memory management exceptions caused by a faulting vector instruction in a vector processor by halting the execution of the faulting vector instruction being executed when the exception occurred and by setting the state information for the vector processor to acknowledge the presence of the exception and to include information about the suboperation of the vector instruction being executed when the exception occurred. The scalar processor is not interrupted at this time, however. Any other vector instructions executing simutaneously with the faulting vector instruction are allowed to continue so long as those instructions do not require data from the faulting instruction. The faulting partially completed vector instruction resumes execution after the operating system has processed the memory management exception.
摘要翻译：数据处理系统通过停止异常发生时执行的故障向量指令的执行，并且通过设置向量处理器的状态信息来确认异常的存在来处理由矢量处理器中的故障向量指令引起的存储器管理异常并且包括关于当异常发生时正在执行的向量指令的子程序的信息。然而，标量处理器此时不会中断。只要这些指令不需要来自故障指令的数据，允许与故障向量指令同时执行的任何其他向量指令。故障部分完成向量指令在操作系统处理内存管理异常后恢复执行。

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