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1. 发明申请

US20150003281A1 SCALABLE MULTI-LAYER 2D-MESH ROUTERS 有权
标题翻译：可扩展的多层2D网路路由器
公开(公告)号：US20150003281A1
公开(公告)日：2015-01-01
申请号：US13927523
申请日：2013-06-26
申请人： William C. Hasenplaugh , Tryggve Fossum , Judson S. Leonard
发明人： William C. Hasenplaugh , Tryggve Fossum , Judson S. Leonard
IPC分类号： H04L12/933 , H04L12/24 , H04L12/733
CPC分类号： H04L49/15 , H04L41/12 , H04L45/12 , H04L45/122 , H04L49/101 , H04L49/25
摘要： Architectures, apparatus and systems employing scalable multi-layer 2D-mesh routers. A 2D router mesh comprises bi-direction pairs of linked paths coupled between pairs of IO interfaces and configured in a plurality of rows and columns forming a 2D mesh. Router nodes are located at the intersections of the rows and columns, and are configured to forward data units between IO inputs and outputs coupled to the mesh at its edges through use of shortest path routes defined by agents at the IO interfaces. Multiple instances of the 2D meshes may be employed to support bandwidth scaling of the router architecture. One implementation of a multi-layer 2D mesh is built using a standard tile that is tessellated to form a 2D array of standard tiles, with each 2D mesh layer offset and overlaid relative to the other 2D mesh layers. IO interfaces are then coupled to the multi-layer 2D mesh via muxes/demuxes and/or crossbar interconnects.
摘要翻译：采用可扩展多层二维网状路由器的架构，设备和系统。 2D路由器网格包括耦合在IO对接口之间的双向对链接路径，并且被配置成形成2D网格的多个行和列。路由器节点位于行和列的交点处，并且被配置为通过使用由IO接口上的代理定义的最短路径路由来在IO输入和耦合到其边缘的网格的输出之间转发数据单元。可以采用2D网格的多个实例来支持路由器架构的带宽缩放。使用被镶嵌的标准瓦片来构建多层2D网格的一个实施方式，以形成标准瓦片的2D阵列，其中每个2D网格层相对于其他2D网格层偏移并重叠。然后，IO接口通过多路复用/解复用和/或交叉连接互连到多层2D网格。

2. 发明申请

US20130173893A1 HARDWARE COMPILATION AND/OR TRANSLATION WITH FAULT DETECTION AND ROLL BACK FUNCTIONALITY 有权
公开(公告)号：US20130173893A1
公开(公告)日：2013-07-04
申请号：US13341812
申请日：2011-12-30
申请人： Nicholas Cheng Hwa Chee , Tryggve Fossum , William C. Hasenplaugh
发明人： Nicholas Cheng Hwa Chee , Tryggve Fossum , William C. Hasenplaugh
IPC分类号： G06F9/318 , G06F9/312
CPC分类号： G06F8/44 , G06F9/3001 , G06F9/30087 , G06F9/30174 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/462 , G06F11/0751
摘要： Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states.

3. 发明申请

US20140189413A1 DISTRIBUTED POWER MANAGEMENT FOR MULTI-CORE PROCESSORS 有权
标题翻译：多核处理器的分布式电源管理
公开(公告)号：US20140189413A1
公开(公告)日：2014-07-03
申请号：US13732289
申请日：2012-12-31
申请人： William C. Hasenplaugh , Tryggve Fossum
发明人： William C. Hasenplaugh , Tryggve Fossum
IPC分类号： G06F1/28
CPC分类号： G06F1/3206 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G06F9/3885 , G06F9/5094 , Y02D10/152 , Y02D10/22
摘要： A system and method for performing distributed power control in a processor comprising an array of cores enables each core to regulate power at least partially independently. Global power management settings are made accessible to all cores and communication between cores propagates power consumption information between nearest neighbors in the array. Each core attempts to best regulate its own power consumption in accordance with global power consumption information and/or specific instructions from a global power manager. In this manner local opportunistic load balancing may be achieved in a scalable manner suitable for a large array of cores.
摘要翻译：用于在包括核心阵列的处理器中执行分布式功率控制的系统和方法使得每个核心能够至少部分地独立地调节功率。所有核心都可以访问全局电源管理设置，并且内核之间的通信会传播阵列中最近邻居之间的功耗信息。每个核心都尝试根据全球功耗信息和/或来自全球电源管理员的特定指令来最佳地调节其自身的功耗。以这种方式，可以以适合于大型核心阵列的可扩展方式来实现本地机会性负载平衡。

4. 发明授权

US08893094B2 Hardware compilation and/or translation with fault detection and roll back functionality 有权
标题翻译：具有故障检测和回滚功能的硬件编译和/或翻译
公开(公告)号：US08893094B2
公开(公告)日：2014-11-18
申请号：US13341812
申请日：2011-12-30
申请人： Nicholas Cheng Hwa Chee , Tryggve Fossum , William C. Hasenplaugh
发明人： Nicholas Cheng Hwa Chee , Tryggve Fossum , William C. Hasenplaugh
IPC分类号： G06F9/45 , G06F7/38 , G06F11/00 , G06F9/38 , G06F9/46 , G06F11/07
CPC分类号： G06F8/44 , G06F9/3001 , G06F9/30087 , G06F9/30174 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/462 , G06F11/0751
摘要： Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states.
摘要翻译：公开了具有故障检测和回滚功能的硬件编译和/或翻译。编译和/或翻译逻辑接收以一种语言编码的程序，并且将该程序编码成包括指令的第二语言，以支持未被编码为程序的原始语言编码的处理器特征。在一个实施例中，执行单元执行包括执行第一操作的操作检查指令的第二语言的指令并记录用于比较的第一操作结果，以及执行第二操作和故障检测操作的操作测试指令通过比较第二操作结果与记录的第一操作结果。在一些实施例中，执行单元执行第二语言的指令，包括提交指令以记录映射到架构寄存器的寄存器的执行检查点状态，以及回滚指令，将映射到架构寄存器的寄存器恢复到先前记录的执行检查点状态。

5. 发明申请

US20140201446A1 HIGH BANDWIDTH FULL-BLOCK WRITE COMMANDS 审中-公开
标题翻译：高带宽全写写命令
公开(公告)号：US20140201446A1
公开(公告)日：2014-07-17
申请号：US13993716
申请日：2011-12-28
申请人： Simon C. Steeley, JR. , William C. Hasenplaugh , Joel S. Emer , Samantika Subramaniam
发明人： Simon C. Steeley, JR. , William C. Hasenplaugh , Joel S. Emer , Samantika Subramaniam
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F13/28
摘要： A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high bandwidth write command. The method may comprise sending a write request from a requester to a record keeping structure. The write request may have a memory address of a memory that stores requested data. The method may further determine copies of the requested data being present in a distributed cache system outside the memory, sending invalidation requests to elements holding copies of the requested data in the distributed cache system, sending a notification to the requester to inform presence of copies of the requested data and sending a write response message after a latest value of the requested data and all invalidation acknowledgements have been received.
摘要翻译：微架构可以提供高带宽写命令的硬件和软件。微架构可以调用执行高带宽写入命令的方法。该方法可以包括从请求者向记录保存结构发送写入请求。写请求可以具有存储请求的数据的存储器的存储器地址。该方法还可以确定存储在存储器外部的分布式高速缓存系统中的所请求数据的副本，向分发的高速缓存系统发送无效请求给保存所请求数据的副本的元件，向请求者发送通知，以通知存在副本所请求的数据和在所请求的数据的最新值和所有无效确认已经被接收之后发送写入响应消息。

6. 发明申请

US20130339621A1 ADDRESS RANGE PRIORITY MECHANISM 有权
标题翻译：地址范围优先机制
公开(公告)号：US20130339621A1
公开(公告)日：2013-12-19
申请号：US13995381
申请日：2011-12-23
申请人： Simon Steely, JR. , Samantika Subramaniam , William C. Hasenplaugh
发明人： Simon Steely, JR. , Samantika Subramaniam , William C. Hasenplaugh
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/1009 , G06F12/1027 , G06F12/1054 , G06F12/126 , G06F12/128 , G06F2212/621 , G06F2212/65 , G06F2212/683
摘要： Method and apparatus to efficiently manage data in caches. Data in caches may be managed based on priorities assigned to the data. Data may be requested by a process using a virtual address of the data. The requested data may be assigned a priority by a component in a computer system called an address range priority assigner (ARP). The ARP may assign a particular priority to the requested data if the virtual address of the requested data is within a particular range of virtual addresses. The particular priority assigned may be high priority and the particular range of virtual addresses may be smaller than a cache's capacity.
摘要翻译：有效管理缓存中的数据的方法和设备。高速缓存中的数据可以基于分配给数据的优先级来管理。数据可以由使用数据的虚拟地址的进程请求。请求的数据可以被称为地址范围优先级分配器（ARP）的计算机系统中的组件分配优先级。如果请求的数据的虚拟地址在虚拟地址的特定范围内，则ARP可以向所请求的数据分配特定优先级。分配的特定优先级可以是高优先级，并且虚拟地址的特定范围可以小于高速缓存的容量。

7. 发明申请

US20130326147A1 SHORT CIRCUIT OF PROBES IN A CHAIN 有权
标题翻译：链中探针的短路
公开(公告)号：US20130326147A1
公开(公告)日：2013-12-05
申请号：US13996012
申请日：2011-12-29
申请人： Simon C. Steely, JR. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, JR. , Samantika Subramaniam , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/082
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining that a local last accessor of the memory address may have a copy of the requested data up to date with the memory. The local last accessor may be within a local domain that the requester belongs to. The method may further comprise sending a cache probe to the local last accessor and retrieving a latest value of the requested data from the local last accessor to the requester.
摘要翻译：多核处理装置可以提供高速缓存探针和数据检索方法。该方法可以包括将请求者的存储器请求发送到记录保存结构。存储器请求可以具有存储请求的数据的存储器的存储器地址。该方法还可以包括确定存储器地址的本地最后访问器可以具有与存储器一起的所请求数据的副本。本地最后一个访问者可能在请求者所属的本地域内。该方法还可以包括向本地最后一个访问器发送高速缓存探测器，并且从本地最后一个访问器检索所请求的数据的最新值到请求者。

8. 发明授权

US07725657B2 Dynamic quality of service (QoS) for a shared cache 有权
标题翻译：共享缓存的动态服务质量（QoS）
公开(公告)号：US07725657B2
公开(公告)日：2010-05-25
申请号：US11726238
申请日：2007-03-21
申请人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
发明人： William C. Hasenplaugh , Li Zhao , Ravishankar Iyer , Ramesh Illikkal , Srihari Makineni , Donald Newell , Aamer Jaleel , Simon C. Steely, Jr.
IPC分类号： G06F12/06
CPC分类号： G06F12/084 , G06F12/0842
摘要： In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于将第一优先级指示符与存储在共享高速缓冲存储器的第一条目中的数据相关联以指示第一线程的优先级，并且将第二优先级指示符与存储的数据相关联的方法在图形引擎的共享高速缓冲存储器的第二条目中指示第二线程的优先级。描述和要求保护其他实施例。

9. 发明申请

US20080075278A1 TECHNIQUES FOR MERGING TABLES 失效
标题翻译：合并表的技术
公开(公告)号：US20080075278A1
公开(公告)日：2008-03-27
申请号：US11534330
申请日：2006-09-22
申请人： Gunnar Gaubatz , William C. Hasenplaugh , Bradley A. Burres , Wajdi Feghali , Kirk Yap
发明人： Gunnar Gaubatz , William C. Hasenplaugh , Bradley A. Burres , Wajdi Feghali , Kirk Yap
IPC分类号： H04L9/30
CPC分类号： H04L9/0618 , G09C1/00 , H04L2209/122
摘要： Techniques are described herein to overlay and merge any number of tables of equivalent size and structure. Bits or patterns of bits that are similar among tables may be set to a voltage value representative of respective logical ‘0’ or ‘1’. The bits that are different among the tables may be connected to either the value of a table selection signal or its inverse.
摘要翻译：这里描述了覆盖和合并任意数目的等效大小和结构的表的技术。可以将表中相似的比特或模式设置为表示相应的逻辑“0”或“1”的电压值。表中不同的位可以连接到表选择信号的值或其反相。

10. 发明授权

US09477610B2 Address range priority mechanism 有权
标题翻译：地址范围优先机制
公开(公告)号：US09477610B2
公开(公告)日：2016-10-25
申请号：US13995381
申请日：2011-12-23
申请人： Simon Steely, Jr. , Samantika Subramaniam , William C. Hasenplaugh
发明人： Simon Steely, Jr. , Samantika Subramaniam , William C. Hasenplaugh
IPC分类号： G06F12/08 , G06F12/12 , G06F12/10
CPC分类号： G06F12/0891 , G06F12/1009 , G06F12/1027 , G06F12/1054 , G06F12/126 , G06F12/128 , G06F2212/621 , G06F2212/65 , G06F2212/683
摘要： Method and apparatus to efficiently manage data in caches. Data in caches may be managed based on priorities assigned to the data. Data may be requested by a process using a virtual address of the data. The requested data may be assigned a priority by a component in a computer system called an address range priority assigner (ARP). The ARP may assign a particular priority to the requested data if the virtual address of the requested data is within a particular range of virtual addresses. The particular priority assigned may be high priority and the particular range of virtual addresses may be smaller than a cache's capacity.
摘要翻译：有效管理缓存中的数据的方法和设备。高速缓存中的数据可以基于分配给数据的优先级来管理。数据可以由使用数据的虚拟地址的进程请求。请求的数据可以被称为地址范围优先级分配器（ARP）的计算机系统中的组件分配优先级。如果请求的数据的虚拟地址在虚拟地址的特定范围内，则ARP可以向所请求的数据分配特定优先级。分配的特定优先级可以是高优先级，并且虚拟地址的特定范围可以小于高速缓存的容量。

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