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2. 发明专利

DE1665064B1 未知
公开(公告)号：DE1665064B1
公开(公告)日：1971-03-04
申请号：DE1665064
申请日：1966-07-29
申请人： MATSUSHITA ELECTRIC WORKS LTD , WATANABE TOSHIO
发明人： WATANABE TOSHIO , UKITA SHIGETSUGU
IPC分类号： H01H9/54 , H01H9/30
摘要： 1,113,732. Arcing preventing in switches. MATSUSHITA DENKO KABUSHIKI KAISHA and T. WATANABE. 28 July, 1966 [30 July, 1965; 18 Aug., 1965], No. 33972/66. Heading H1N. An arc suppressing arrangement for use with a pair of contacts (SW) used to interrupt an alternating current comprises a two-terminal multi-layer semi-conductor device (SSS) across the contacts (Fig. 3, not shown). The device (SSS) is a five-layer diode, and a series combination of a capacitor (C) and resistor (R) is inserted in parallel with the switch (SW) and load (L) to protect the diode against voltage surges (Fig. 4, not shown), or is alternatively in parallel with the diode (SSS), (Fig. 5, not shown). An inductor (L 1 ) may be connected in series with the device (SSS), (Figs. 6, 7, not shown), to restrict the current therethrough. The secondary winding (L2) of a transformer (T) is connected in series with the device (SSS), the primary winding (L1) being in series with a capacitor (C1) and the combination being connected across the switch contacts. A voltage surge-limiting capacitor (C2) is optionally provided (Figs. 8-15, not shown).

4. 发明专利

GB1126570A Arc-suppressing circuit for switching devices in direct current circuit 未知
公开(公告)号：GB1126570A
公开(公告)日：1968-09-05
申请号：GB4215166
申请日：1966-09-21
申请人： MATSUSHITA ELECTRIC WORKS LTD , TOSHIO WATANABE
发明人： WATANABE TOSHIO , UKITA SHIGETSUGU
IPC分类号： H01H9/54
摘要： 1,126,570. Arcing preventing in switches. MATSUSHITA DENKO K.K., and T. WATANABE. 21 Sept., 1966 [30 Oct., 1965], No. 42151/66. Heading H1N. A two-terminal multi-layer semi-conductor element SSS in series with a capacitor C or resistor R (Fig. 5, not shown), is placed across the contacts of a D.C. switch SW to suppress arcing. The switch contacts are in series with a load Z, and the Fig. 5 circuit is used only when other contacts (not shown) are connected in series and the load is interrupted at these other (latter) contacts. The capacitor C has a discharge resistor (R 1 ) in parallel therewith to aid quick discharge of the capacitor (Fig. 3, not shown). An inductor (L) in series with element SSS protects against voltage surges (Fig. 3, not shown). A resistance (R) may be connected between element (SSS) and the live side of the contacts, and an inductor (L) placed in parallel with capacitor (C), (Fig. 4, not shown). The circuit of Fig. 5 may have a capacitor or inductor conductor in parallel with elements SSS (Figs. 6, 7, not shown).

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