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1. 发明授权

US07902879B2 Field programmable gate array utilizing dedicated memory stacks in a vertical layer format 有权
标题翻译：利用垂直层格式的专用存储器堆栈的现场可编程门阵列
公开(公告)号：US07902879B2
公开(公告)日：2011-03-08
申请号：US12639625
申请日：2009-12-16
申请人： Volkan H. Ozguz , Randolph S. Carlson , Keith D. Gann , John Leon , W. Eric Boyd
发明人： Volkan H. Ozguz , Randolph S. Carlson , Keith D. Gann , John Leon , W. Eric Boyd
IPC分类号： H01L25/00 , H03K19/00
CPC分类号： H03K19/1776 , G01R31/318519 , G06F9/3802 , H03K19/177 , H03K19/17792
摘要： A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.
摘要翻译：现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。绝对最大字宽度可以与m * N一样大，其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。

2. 发明授权

US07649386B2 Field programmable gate array utilizing dedicated memory stacks in a vertical layer format 有权
标题翻译：利用垂直层格式的专用存储器堆栈的现场可编程门阵列
公开(公告)号：US07649386B2
公开(公告)日：2010-01-19
申请号：US11897938
申请日：2007-08-31
申请人： Volkan H. Ozguz , Randolph S. Carlson , Keith D. Gann , John Leon , W. Eric Boyd
发明人： Volkan H. Ozguz , Randolph S. Carlson , Keith D. Gann , John Leon , W. Eric Boyd
IPC分类号： H01L25/00 , H03K19/00
CPC分类号： H03K19/1776 , G01R31/318519 , G06F9/3802 , H03K19/177 , H03K19/17792
摘要： A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.
摘要翻译：现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。绝对最大字宽度可以与m.times.N一样大m其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。

3. 发明申请

US20100148822A1 FIELD PROGRAMMABLE GATE ARRAY UTILIZING DEDICATED MEMORY STACKS IN A VERTICAL LAYER FORMAT 有权
标题翻译：现场可编程门阵列使用垂直层格式中的专用存储堆栈
公开(公告)号：US20100148822A1
公开(公告)日：2010-06-17
申请号：US12639625
申请日：2009-12-16
申请人： Volkan H. Ozguz , Randolph S. Carlson , Keith D. Gann , John Leon , W. Eric Boyd
发明人： Volkan H. Ozguz , Randolph S. Carlson , Keith D. Gann , John Leon , W. Eric Boyd
IPC分类号： H03K19/00
CPC分类号： H03K19/1776 , G01R31/318519 , G06F9/3802 , H03K19/177 , H03K19/17792
摘要： A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.
摘要翻译：现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。绝对最大字宽度可以与m * N一样大，其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。

4. 发明授权

US07777321B2 Stacked microelectronic layer and module with three-axis channel T-connects 失效
标题翻译：堆叠的微电子层和模块具有三轴通道T型连接
公开(公告)号：US07777321B2
公开(公告)日：2010-08-17
申请号：US11259683
申请日：2005-10-25
申请人： Keith D. Gann , W. Eric Boyd
发明人： Keith D. Gann , W. Eric Boyd
IPC分类号： H01L23/495
CPC分类号： H01L25/50 , H01L25/0657 , H01L2225/0651 , H01L2225/06524 , H01L2225/06551 , H01L2225/06572 , H01L2924/0002 , H01L2924/00
摘要： A method for interconnecting stacked layers containing integrated circuit die and a device built from the method is disclosed. The stacked layers are bonded together to form a module whereby individual I/O pads of the integrated circuit die are rerouted to at least one edge of the module. The rerouted leads terminate at the edge. Channels are formed in a surface of the module or on the surface of a layer whereby the rerouted leads are disposed within the channel. The entire surface of the edge or layer is metalized and a predetermined portion of the metalization removed such that the rerouted leads within each channel are electrically connected to each other.
摘要翻译：公开了一种用于将包含集成电路管芯的堆叠层互连的方法和由该方法构建的器件。堆叠的层被结合在一起以形成模块，由此集成电路管芯的各个I / O焊盘被重新路由到模块的至少一个边缘。重新路由的引线终止于边缘。通道形成在模块的表面或层的表面上，由此重新布线的引线设置在通道内。边缘或层的整个表面被金属化，去除金属化的预定部分，使得每个通道内的重新引导的引线彼此电连接。

5. 发明申请

US20120185636A1 Tamper-Resistant Memory Device With Variable Data Transmission Rate 审中-公开
标题翻译：具有可变数据传输速率的防篡改存储器件
公开(公告)号：US20120185636A1
公开(公告)日：2012-07-19
申请号：US13363571
申请日：2012-02-01
申请人： John Leon , W. Eric Boyd , Sambo He , Christian Krutzik
发明人： John Leon , W. Eric Boyd , Sambo He , Christian Krutzik
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： H01L23/576 , H01L23/3107 , H01L25/0657 , H01L2224/16145 , H01L2224/16265 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/1432 , H01L2924/1434 , H01L2924/19041 , H01L2924/19103 , H01L2924/19107 , H01L2924/3011
摘要： A high capacity, secure and tamper-resistant computer data memory device. The device uses a plurality of dedicated memory controller elements in communication with an anti-tamper module that generates a tamper response when a predetermined tamper event occurs. The tamper response may be provided as the erasure or zeroization of the contents of a memory in the devices such as erasing one or more encryption keys. The elements of the device are preferably provided in a stacked configuration with rerouted I/O pads to obfuscate the I/O and function of the devices in the stack. In one embodiment, a data transfer governance means is provided. In a further embodiment, a current negotiation means is disclosed to permit the device to request a predetermined current from a host device. In a yet further embodiment, a portable safe house computing device is provided.
摘要翻译：高容量，安全和防篡改的计算机数据存储设备。该装置使用与防篡改模块通信的多个专用存储器控制器元件，当预定的篡改事件发生时，该防篡改模块产生篡改响应。篡改响应可以被提供为擦除或零化设备中的存储器的内容，例如擦除一个或多个加密密钥。器件的元件优选地以具有重新路由的I / O焊盘的堆叠配置提供，以模糊堆叠中的I / O和功能。在一个实施例中，提供了数据传送治理装置。在另一个实施例中，公开了当前的协商手段，以允许设备从主机设备请求预定的电流。在又一实施例中，提供了一种便携式安全屋计算装置。

6. 发明申请

US20120068333A1 Wire Bond Through-Via Structure and Method 有权
标题翻译：电线键合通孔结构和方法
公开(公告)号：US20120068333A1
公开(公告)日：2012-03-22
申请号：US13209898
申请日：2011-08-15
申请人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi
发明人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi
IPC分类号： H01L23/488 , H01L21/56
CPC分类号： H01L24/45 , H01L21/568 , H01L23/498 , H01L23/49811 , H01L24/05 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/105 , H01L2224/04042 , H01L2224/45144 , H01L2224/45541 , H01L2224/82001 , H01L2224/96 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/18162 , H01L2924/19107 , H01L2924/3011 , H01L2224/82 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/48
摘要： A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
摘要翻译：一种可堆叠的集成电路芯片层和模块装置，其避免了在包含集成电路管芯的层的外表面上使用导电元件，利用常规引线键合设备来提供由引线键合段限定的导电路径，封装在灌封材料中，以便限定可从该层的至少下表面或第二表面接近的导电引线键合“通孔”。

7. 发明授权

US09431275B2 Wire bond through-via structure and method 有权
标题翻译：引线键合通孔结构和方法
公开(公告)号：US09431275B2
公开(公告)日：2016-08-30
申请号：US13209898
申请日：2011-08-15
申请人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi , Angel Pepe
发明人： Randy Bindrup , W. Eric Boyd , John Leon , James Yamaguchi , Angel Pepe
IPC分类号： H01L23/488 , H01L21/56 , H01L23/00 , H01L25/10
CPC分类号： H01L24/45 , H01L21/568 , H01L23/498 , H01L23/49811 , H01L24/05 , H01L24/24 , H01L24/82 , H01L24/96 , H01L25/105 , H01L2224/04042 , H01L2224/45144 , H01L2224/45541 , H01L2224/82001 , H01L2224/96 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/18162 , H01L2924/19107 , H01L2924/3011 , H01L2224/82 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/48
摘要： A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
摘要翻译：一种可堆叠的集成电路芯片层和模块装置，其避免了在包含集成电路管芯的层的外表面上使用导电元件，利用常规引线键合设备来提供由引线键合段限定的导电路径，封装在灌封材料中，以便限定可从该层的至少下表面或第二表面接近的导电引线键合“通孔”。

8. 发明申请

US20110227603A1 Secure Anti-Tamper Integrated Layer Security Device Comprising Nano-Structures 审中-公开
标题翻译：包含纳米结构的安全防篡改集成层安全设备
公开(公告)号：US20110227603A1
公开(公告)日：2011-09-22
申请号：US13045880
申请日：2011-03-11
申请人： John Leon , James Yamaguchi , W. Eric Boyd , Volkan Ozguz
发明人： John Leon , James Yamaguchi , W. Eric Boyd , Volkan Ozguz
IPC分类号： H03K19/00 , H02H3/08 , G01R27/26 , G01R27/08
CPC分类号： H01L23/576 , H01L24/24 , H01L25/0657 , H01L25/16 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/3011 , H01L2924/00
摘要： A device and method using one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. The nano-structure is in connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the nano-structure is breached or altered. One or more electrically conductive nano-structures interconnect and reroute one or more electrical connections between one or more ICs to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device. microscope.
摘要翻译：限定在微电子电路的一个或多个表面上的一个或多个导电纳米结构的装置和方法，所述微电子电路例如集成电路管芯，微电子电路封装堆叠的微电子电路封装，或者在一个或多个层的表面上一堆包含一个或多个IC的层。纳米结构与监控电路相连，并用作“跳闸线”，以检测未经授权篡改设备或模块。这种监视电路可以包括芯片或封装内的诸如电路内或模块内电池的电源和“归零”电路，以在纳米结构被破坏或改变时擦除存储器的内容物。一个或多个导电纳米结构互连并重新路由一个或多个IC之间的一个或多个电连接，以在芯片或堆栈上产生“不可见”的电连接集合，以模糊设备的反向工程尝试。显微镜。

9. 发明申请

US20110031982A1 Tamper-resistant electronic circuit and module incorporating electrically conductive nano-structures 审中-公开
标题翻译：具有防篡改电子电路和包含导电纳米结构的模块
公开(公告)号：US20110031982A1
公开(公告)日：2011-02-10
申请号：US12806127
申请日：2010-08-04
申请人： John Leon , James Yamaguchi , Volkan Ozguz , W. Eric Boyd
发明人： John Leon , James Yamaguchi , Volkan Ozguz , W. Eric Boyd
IPC分类号： G01R27/28 , H02H3/08 , H05K7/00
CPC分类号： H01L23/576 , H01L25/0657 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device and method are disclosed comprising one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package (such as a TSOP, BGA or other prepackaged IC) a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs.In one embodiment, the electrically conductive nano-structure is in electrical connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the electrically conductive nano-structure is breached or altered. The device may be configured to blow one or more fuses or overcurrent protection devices when the electrically conductive nano-structure is breached or altered.In a further embodiment, one or more electrically conductive nano-structures are used to interconnect and reroute one or more electrical connections between one or more ICs (or dummy leads and vias) to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device, i.e., a set of connections that cannot be observed by standard test means such as by X-ray or conventional microscope.
摘要翻译：公开了一种器件和方法，其包括限定在微电子电路的一个或多个表面上的一个或多个导电纳米结构，例如集成电路管芯，微电子电路封装（例如TSOP，BGA或其它预封装IC）堆叠微电子或者在包含一个或多个IC的层叠层中的一个或多个层的表面上。在一个实施例中，导电纳米结构与监控电路电连接，并用作“跳闸线”，以检测未经授权的篡改设备或模块。这样的监视电路可以包括诸如电路内或模块内电池的电源和芯片或封装内的“零化”电路，以在导电纳米结构被破坏或改变时擦除存储器的内容物。该装置可以被配置为当导电纳米结构被破坏或改变时吹送一个或多个保险丝或过电流保护装置。在另一个实施例中，使用一个或多个导电纳米结构来互连和重新路由一个或多个IC（或虚拟引线和通孔）之间的一个或多个电连接，以在芯片上产生“不可见”的电连接集合，或堆叠以模糊化设备的反向工程，即通过X射线或常规显微镜的标准测试手段无法观察到的一组连接。

10. 发明申请

US20120094092A1 Method for Defining an Electronically Conductive Metal Structure on a Three-Dimensional Element and a Device Made From the Method 有权
标题翻译：用于定义三维元件上的电子导电金属结构的方法和由该方法制成的器件
公开(公告)号：US20120094092A1
公开(公告)日：2012-04-19
申请号：US13267651
申请日：2011-10-06
申请人： James Yamaguchi , W. Eric Boyd
发明人： James Yamaguchi , W. Eric Boyd
IPC分类号： B32B3/00 , G03F7/20
CPC分类号： B32B15/16 , B32B2559/00
摘要： A method for defining an electrically conductive metalized structure, which may comprise an electrode or trace, on the surface of a three-dimensional element. The three-dimensional element may comprise a glass microsphere or shell resonator. A laser direct write grayscale photolithographic process is used in conjunction with electrically conductive metal deposition processes to define one or more electrically conductive metal structures on the surfaces of the three dimensional element.
摘要翻译：一种用于在三维元件的表面上限定可以包括电极或迹线的导电金属化结构的方法。三维元件可以包括玻璃微球或壳谐振器。激光直写式灰度光刻工艺与导电金属沉积工艺结合使用以在三维元件的表面上限定一个或多个导电金属结构。

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