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1. 发明授权

US06976131B2 Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system 有权
标题翻译：用于芯片多处理器或多处理器系统的共享高速缓存一致性的方法和装置
公开(公告)号：US06976131B2
公开(公告)日：2005-12-13
申请号：US10226478
申请日：2002-08-23
申请人： Vladimir Pentkovski , Vivek Garg , Narayanan S. Iyer , Jagannath Keshava
发明人： Vladimir Pentkovski , Vivek Garg , Narayanan S. Iyer , Jagannath Keshava
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831
摘要： A method and apparatus for shared cache coherency for a chip multiprocessor or a multiprocessor system. In one embodiment, a multicore processor includes a plurality of processor cores, each having a private cache, and a shared cache. An internal snoop bus is coupled to each private cache and the shared cache to communicate data from each private cache to other private caches and the shared cache. In another embodiment, an apparatus includes a plurality of processor cores and a plurality of caches. One of the plurality of caches maintains cache lines in two different modified states. The first modified state indicates a most recent copy of a modified cache line, and the second modified state indicates a stale copy of the modified cache line.
摘要翻译：一种用于芯片多处理器或多处理器系统的共享高速缓存一致性的方法和装置。在一个实施例中，多核处理器包括多个处理器核，每个具有专用高速缓存和共享高速缓存。内部监听总线耦合到每个专用高速缓存和共享高速缓存，以将数据从每个专用高速缓存传送到其他专用高速缓存和共享高速缓存。在另一个实施例中，一种装置包括多个处理器核和多个高速缓存。多个高速缓存之一将高速缓存行维持在两个不同的修改状态。第一修改状态指示经修改的高速缓存行的最新副本，并且第二修改状态指示经修改的高速缓存行的过时副本。

2. 发明授权

US06643745B1 Method and apparatus for prefetching data into cache 失效
标题翻译：将数据预取到高速缓存中的方法和装置
公开(公告)号：US06643745B1
公开(公告)日：2003-11-04
申请号：US09053383
申请日：1998-03-31
申请人： Salvador Palanca , Niranjan L. Cooray , Angad Narang , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran , Jagannath Keshava , Hsien-Hsin Lee , Steve Spangler , Suresh Kuttuva , Praveen Mosur
发明人： Salvador Palanca , Niranjan L. Cooray , Angad Narang , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran , Jagannath Keshava , Hsien-Hsin Lee , Steve Spangler , Suresh Kuttuva , Praveen Mosur
IPC分类号： G06F1200
CPC分类号： G06F9/383 , G06F9/3842 , G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.
摘要翻译：公开了一种计算机系统。计算机系统包括较高级别的缓存，较低级别的缓存，解码指令的解码器以及耦合到解码器的电路。在一个实施例中，电路响应于单个解码的指令，在较高级别的高速缓存未命中时从外部存储器检索数据并绕过下一级高速缓存。在另一个实施例中，电路响应于第一解码指令发出从外部存储器的地址检索数据的请求，以将所述数据仅放置在较低级别的高速缓存中，检测到所述地址的第二可缓存解码指令，表示高级缓存中的数据。

3. 发明授权

US06978357B1 Method and apparatus for performing cache segment flush and cache segment invalidation operations 失效
标题翻译：用于执行高速缓存段刷新和缓存段无效操作的方法和装置
公开(公告)号：US06978357B1
公开(公告)日：2005-12-20
申请号：US09122349
申请日：1998-07-24
申请人： Lance Hacking , Shreekant Thakkar , Thomas Huff , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
发明人： Lance Hacking , Shreekant Thakkar , Thomas Huff , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804
摘要： A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.
摘要翻译：一种用于在计算机系统中包括用于执行高速缓存存储器无效的指令和高速缓存存储器刷新操作的方法和装置。在一个实施例中，计算机系统包括具有存储数据的多个高速缓存行和存储数据操作数的存储区域的高速缓冲存储器。执行单元耦合到存储区域，并且响应于接收到单个指令，对数据操作数中的数据元素进行操作以使多个高速缓存行的预定部分中的数据无效。

4. 发明申请

US20050216706A1 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US20050216706A1
公开(公告)日：2005-09-29
申请号：US11126049
申请日：2005-05-09
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant Thakkar
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.
摘要翻译：提供了一种用于执行打包数据指令的方法和装置。根据本发明的一个方面，处理器包括寄存器，耦合到寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件来存储包括数据元素的打包数据操作数。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组中的每个指令指定要对所有数据元素执行的操作。相比之下，第二组中的每个指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

5. 发明授权

US06356270B2 Efficient utilization of write-combining buffers 失效
标题翻译：高效利用写入组合缓冲区
公开(公告)号：US06356270B2
公开(公告)日：2002-03-12
申请号：US09053231
申请日：1998-03-31
申请人： Vladimir Pentkovski , Hsien-Cheng E. Hsieh , Hsien-Hsin Lee , Subramaniam Maiyuran
发明人： Vladimir Pentkovski , Hsien-Cheng E. Hsieh , Hsien-Hsin Lee , Subramaniam Maiyuran
IPC分类号： G06T160
CPC分类号： G06F9/30043 , G06F9/3824 , G06F12/0875
摘要： The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.
摘要翻译：本发明公开了一种用于对分散位置的非时间存储序列的写合成缓冲器有效利用的方法和装置方法。该方法包括：将非时间存储序列转换为存储到中间缓冲器; 并将商店分组到中间缓冲器到连续的非时间商店。连续的非时间存储对应于写合成缓冲器中的相邻存储器位置。

6. 发明授权

US06223258B1 Method and apparatus for implementing non-temporal loads 失效
标题翻译：用于实现非时间载荷的方法和装置
公开(公告)号：US06223258B1
公开(公告)日：2001-04-24
申请号：US09053528
申请日：1998-03-31
申请人： Salvador Palanca , Vladimir Pentkovski , Steve Tsai
发明人： Salvador Palanca , Vladimir Pentkovski , Steve Tsai
IPC分类号： G06F1212
CPC分类号： G06F9/30043 , G06F9/3802 , G06F9/3814 , G06F9/3832 , G06F12/0875 , G06F12/0888
摘要： A processor is described. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, to detect an incoming load instruction that misses a cache, allocate a buffer to service the incoming load instruction, and issue a bus request to load the data in the buffer without accessing said cache.
摘要翻译：描述处理器。所述处理器包括解码器，用于响应于解码指令来解码指令和电路，以检测错过高速缓存的输入加载指令，分配缓冲器来服务输入加载指令，并发出总线请求以将数据加载到缓冲区不访问所述缓存。

7. 发明授权

US6085312A Method and apparatus for handling imprecise exceptions 失效
标题翻译：处理不精确异常的方法和装置
公开(公告)号：US6085312A
公开(公告)日：2000-07-04
申请号：US052994
申请日：1998-03-31
申请人： Mohammad Abdallah , Vladimir Pentkovski
发明人： Mohammad Abdallah , Vladimir Pentkovski
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38 , G06F9/40
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30145 , G06F9/3017 , G06F9/3857 , G06F9/3861
摘要： A method and apparatus for updating the architectural state in a system implementing staggered execution with multiple micro-instructions. According to one aspect of the invention, a method is provided in which a macro-instruction is decoded into a first and second micro-instructions. The macro-instruction designates an operation on a pieced of data, and execution of the first and second micro-instructions separately cause the operation to be performed on different parts of the piece of data. The method also requires that the first micro-instruction is executed irrespective of the second micro-instructions (e.g., at a different time), and that it is detected that said second micro-instruction will not cause any non-recoverable exceptions. The results of the first micro-instruction are then used to update the architectural state in an earlier clock cycle than said second micro-instruction.
摘要翻译：一种用于利用多个微指令来实现交错执行的系统中的架构状态的更新的方法和装置。根据本发明的一个方面，提供一种方法，其中宏指令被解码为第一和第二微指令。宏指令指定对接头数据的操作，并且第一和第二微指令的执行分别导致在该数据段的不同部分上执行操作。该方法还要求与第二微指令（例如，在不同的时间）无论执行第一微指令，并且检测到所述第二微指令不会引起任何不可恢复的异常。然后，第一微指令的结果用于在比所述第二微指令更早的时钟周期内更新架构状态。

8. 发明授权

US08065555B2 System and method for error correction in cache units 有权
标题翻译：高速缓存单元纠错系统及方法
公开(公告)号：US08065555B2
公开(公告)日：2011-11-22
申请号：US11363150
申请日：2006-02-28
申请人： Subramaniam Maiyuran , Varghese George , Vladimir Pentkovski , Sanjib Sarkar , Marina Sherman
发明人： Subramaniam Maiyuran , Varghese George , Vladimir Pentkovski , Sanjib Sarkar , Marina Sherman
IPC分类号： G06F11/00
CPC分类号： G06F11/1064
摘要： A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.
摘要翻译：方法和处理器可以包括将数据阵列中的第一组数据存储在高速缓存单元中，基本上同时从数据阵列读取第二组数据，并且使用第二组数据来生成对应于第一组数据。方法或处理器可以包括从处理器中的高速缓存读取条目，并且基本同时地在条目上执行两个或更多个错误检测机制。

9. 发明申请

US20070226589A1 System and method for error correction in cache units 有权
标题翻译：高速缓存单元纠错系统及方法
公开(公告)号：US20070226589A1
公开(公告)日：2007-09-27
申请号：US11363150
申请日：2006-02-28
申请人： Subramaniam Maiyuran , Varghese George , Vladimir Pentkovski , Sanjib Sarkar , Marina Sherman
发明人： Subramaniam Maiyuran , Varghese George , Vladimir Pentkovski , Sanjib Sarkar , Marina Sherman
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.
摘要翻译：方法和处理器可以包括将数据阵列中的第一组数据存储在高速缓存单元中，基本上同时从数据阵列读取第二组数据，并且使用第二组数据来生成对应于第一组数据。方法或处理器可以包括从处理器中的高速缓存读取条目，并且基本同时地在条目上执行两个或更多个错误检测机制。

10. 发明授权

US06970994B2 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US06970994B2
公开(公告)日：2005-11-29
申请号：US09852217
申请日：2001-05-08
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.
摘要翻译：讨论了用于执行部分宽度打包数据指令的方法和装置。处理器可以包括多个寄存器，寄存器重命名单元，解码器和部分宽度执行单元。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相比之下，第二组指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

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