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1. 发明申请

US20050242371A1 High current MOS device with avalanche protection and method of operation 审中-公开
标题翻译：大电流MOS器件具有雪崩保护和操作方法
公开(公告)号：US20050242371A1
公开(公告)日：2005-11-03
申请号：US10836730
申请日：2004-04-30
申请人： Vishnu Khemka , Amitava Bose , Vijay Parthasarathy , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Vijay Parthasarathy , Ronghua Zhu
IPC分类号： H01L27/07 , H01L29/08 , H01L29/423 , H01L29/78 , H01L31/113
CPC分类号： H01L29/0847 , H01L27/0722 , H01L29/42368 , H01L29/7835
摘要： Particularly in high current applications, impact ionization induced electron-hole pairs are generated in the drain of an MOS transistor that can cause a parasitic bipolar transistor to become destructively conductive. The holes pass through the body region of the MOS transistor, which has intrinsic resistance, to the source, which is typically held at a relatively low voltage, such as ground. The hole current causes a voltage to develop in the body region, which acts as the base. This increased base voltage is what can cause the parasitic bipolar transistor to become conductive. The likelihood of this is greatly reduced by developing a voltage between the source, which acts as the emitter, and the body region by passing the channel current through an impedance between the source and the body region. This causes the emitter voltage to increase as the base voltage is increased and thereby prevent the parasitic bipolar transistor from becoming conductive.
摘要翻译：特别是在高电流应用中，在MOS晶体管的漏极中产生电子 - 电子碰撞的碰撞对，这可使寄生双极晶体管变得具有破坏性的导电性。这些孔通过具有固有电阻的MOS晶体管的体区通向保持在较低电压（例如地）的源极。空穴电流导致在作为基底的身体区域中产生电压。这种增加的基极电压可以导致寄生双极晶体管导通。通过使通道电流通过源极和体区之间的阻抗，在作为发射极的源与体区之间形成电压，大大降低了这种可能性。这导致发射极电压随着基极电压的增加而增加，从而防止寄生双极晶体管导通。

2. 发明授权

US06930027B2 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US06930027B2
公开(公告)日：2005-08-16
申请号：US10369874
申请日：2003-02-18
申请人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui , Michael C. Butner
发明人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui , Michael C. Butner
IPC分类号： H01L21/308 , H01L21/762 , H01L21/425
CPC分类号： H01L21/3081 , H01L21/76229
摘要： A method of manufacturing a semiconductor component includes forming a first electrically insulating layer (120) and a second electrically insulating layer (130) over a semiconductor substrate (110). The method further includes etching a first trench (140) and a second trench (150) through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench (610) through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion (920) and a second portion (930) interior to the first portion. The method still further includes forming a third electrically insulating layer (910) filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer (1010) in the second portion of the third trench.
摘要翻译：制造半导体部件的方法包括在半导体衬底（110）上形成第一电绝缘层（120）和第二电绝缘层（130）。该方法还包括通过第一和第二电绝缘层蚀刻第一沟槽（140）和第二沟槽（150）并进入半导体衬底，以及通过第二沟槽的底表面蚀刻第三沟槽（610）并且进入半导体衬底。第三沟槽在第一部分内部具有第一部分（920）和第二部分（930）。该方法还包括形成填充第一沟槽和第三沟槽的第一部分的第三电绝缘层（910），而不填充第三沟槽的第二部分，并且还包括在第二部分中形成插塞层（1010）的第三沟。

3. 发明授权

US07309638B2 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US07309638B2
公开(公告)日：2007-12-18
申请号：US11182597
申请日：2005-07-14
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L21/20 , H01L21/00
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译：半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320），340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。

4. 发明申请

US20060244081A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20060244081A1
公开(公告)日：2006-11-02
申请号：US11426815
申请日：2006-06-27
申请人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Vijay Parthasarathy
发明人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Vijay Parthasarathy
IPC分类号： H01L29/76
CPC分类号： H01L29/7391 , H01L29/861
摘要： In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).
摘要翻译：在一个实施例中，半导体器件10包括使用隔离区域（34,16和13）和多个掺杂剂浓度（30,20,24和26）的二极管，其可用于限制注入的寄生电流进入半导体基板（12）。可以使用隔离区域（34,16和13）上的各种偏压来影响半导体器件（10）的行为。此外，可以形成覆盖在阳极（42）和阴极（40）之间的连接处的导电层（28）。为了增加施加到阴极（40）的最大电压，该导电层（28）可以减小选定区域中的电场。

5. 发明申请

US20060014342A1 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US20060014342A1
公开(公告)日：2006-01-19
申请号：US11182597
申请日：2005-07-14
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd Roggenbauer
IPC分类号： H01L21/8234 , H01L21/8222 , H01L21/20
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译：半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320），340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。

6. 发明申请

US20060001057A1 Schottky device and method of forming 有权
标题翻译：肖特基器件和成型方法
公开(公告)号：US20060001057A1
公开(公告)日：2006-01-05
申请号：US10881678
申请日：2004-06-30
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L29/80 , H01L21/338
CPC分类号： H01L29/66143 , H01L29/812 , H01L29/872
摘要： A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the first conductivity type immediately underlies the second region and is electrically coupled to a cathode of the device.
摘要翻译：导电层包括形成具有第一导电类型的下面的第一区域的肖特基区域的第一部分。第二导电类型的第二区域位于第一区域的正下方，其中第二导电类型与第一导电类型相反。第一导电类型的第三区域刚好在第二区域的下面，并且电耦合到器件的阴极。

7. 发明授权

US06933546B2 Semiconductor component 有权
标题翻译：半导体元件
公开(公告)号：US06933546B2
公开(公告)日：2005-08-23
申请号：US10391040
申请日：2003-03-17
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L27/02 , H01L27/08 , H01L29/866 , H01L31/0328 , H01L31/328
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译：半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320），340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。

8. 发明授权

US06882023B2 Floating resurf LDMOSFET and method of manufacturing same 有权
标题翻译： LDMOSFET浮法晶体管及其制造方法
公开(公告)号：US06882023B2
公开(公告)日：2005-04-19
申请号：US10286169
申请日：2002-10-31
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L29/06 , H01L29/10 , H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/1083 , H01L29/42368 , H01L29/66681 , H01L29/7835
摘要： A semiconductor component includes a RESURF transistor (100, 200, 300, 400, 500) that includes a first semiconductor region (110, 210, 310, 410, 510) having a first conductivity type and an electrically-floating semiconductor region (115, 215, 315, 415, 515, 545) having a second conductivity type located above the first semiconductor region. The RESURF transistor further includes a second semiconductor region (120, 220, 320, 420, 520) having the first conductivity type located above the electrically-floating semiconductor region, a third semiconductor region (130, 230) having the first conductivity type located above the second semiconductor region, and a fourth semiconductor region (140, 240, 340, 440, 540) having the second conductivity type located above the second semiconductor region. In a particular embodiment, the fourth semiconductor region and the electrically-floating semiconductor region deplete the second semiconductor region when a reverse bias is applied between the third semiconductor region and the fourth semiconductor region.
摘要翻译：半导体部件包括RESURF晶体管（100,200,300,400,500），其包括具有第一导电类型的第一半导体区域（110,210,310,410,510）和电浮置半导体区域（115， 215,315,415,515,545），其具有位于所述第一半导体区域上方的第二导电类型。 RESURF晶体管还包括具有位于电浮置半导体区域上方的第一导电类型的第二半导体区域（120,220,320,420,520），具有位于上方的第一导电类型的第三半导体区域（130,230）第二半导体区域以及具有位于第二半导体区域上方的第二导电类型的第四半导体区域（140,240,340,440,540）。在特定实施例中，当在第三半导体区域和第四半导体区域之间施加反向偏压时，第四半导体区域和电浮置半导体区域耗尽第二半导体区域。

9. 发明授权

US06703895B1 Semiconductor component and method of operating same 有权
标题翻译：半导体元件及其操作方法
公开(公告)号：US06703895B1
公开(公告)日：2004-03-09
申请号：US10256820
申请日：2002-09-26
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L2500
CPC分类号： H01L29/7816 , H01L29/4238 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of a method of redistributing power in a semiconductor component includes varying a saturation current between a drain terminal (330) and a source terminal (320) of a field effect transistor (FET) (200, 500). The FET is at least a portion of the semiconductor component. The threshold voltage of the FET is maintained substantially constant across the FET while the drain-to-source saturation current per unit area is varied across the FET. In one embodiment, the drain-to-source saturation current per unit area is varied such that it is lower at a center of the FET than at a periphery of the FET. In particular embodiments, the drain-to-source saturation current per unit area may be varied across the FET by changing one or more of the gate-to-source voltage, the channel length, the channel width, the gate oxide thickness, and the channel mobility across the FET.
摘要翻译：在半导体部件中重新分配功率的方法的实施例包括改变场效应晶体管（FET）（200,500）的漏极端子（330）和源极端子（320）之间的饱和电流。 FET是半导体部件的至少一部分。 FET的阈值电压在整个FET上保持基本恒定，同时跨FET的每单位面积的漏极 - 源极饱和电流是变化的。在一个实施例中，每单位面积的漏极 - 源极饱和电流是变化的，使得其在FET的中心处比在FET的周边处更低。在特定实施例中，通过改变栅极 - 源极电压，沟道长度，沟道宽度，栅极氧化物厚度和栅极 - 源极电压之间的一个或多个，可以跨FET跨越每单位面积的漏极 - 源极饱和电流 FET上的通道迁移率。

10. 发明授权

US06693339B1 Semiconductor component and method of manufacturing same 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US06693339B1
公开(公告)日：2004-02-17
申请号：US10389401
申请日：2003-03-14
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L2972
CPC分类号： H01L29/7816 , H01L29/0615 , H01L29/0847 , H01L29/0878 , H01L29/7835
摘要： A semiconductor component includes a first semiconductor region (110, 210) having a first conductivity type and a second semiconductor region (120, 220) above the first semiconductor region and having a second conductivity type. The semiconductor component further comprises a third semiconductor region (130, 230) above the second semiconductor region and having the first conductivity type, a fourth semiconductor region (140, 240) above the third semiconductor region and having the second conductivity type, a fifth semiconductor region (150, 250) above the third semiconductor region and having the first conductivity type, a sixth semiconductor region (160, 260) substantially enclosed within the fifth semiconductor region and having the second conductivity type, and a seventh semiconductor region (170, 270) above the first semiconductor region and having the second conductivity type. The seventh semiconductor region is adjacent to the third and fourth semiconductor regions, and is separated from the fifth semiconductor region.
摘要翻译：半导体部件包括具有第一导电类型的第一半导体区域（110,210）和位于第一半导体区域上方并且具有第二导电类型的第二半导体区域（120,220）。半导体部件还包括在第二半导体区域上方并具有第一导电类型的第三半导体区域（130,230），在第三半导体区域上方具有第二导电类型的第四半导体区域（140,240），第五半导体区域具有第一导电类型的第一半导体区域（150,250），基本上封装在第五半导体区域内并且具有第二导电类型的第六半导体区域（160,260）和第七半导体区域（170,270）），并且具有第二导电类型。第七半导体区域与第三和第四半导体区域相邻，并且与第五半导体区域分离。

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