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1. 发明授权

US08294500B1 Multi-phase interpolators and related methods 有权
标题翻译：多相内插器及相关方法
公开(公告)号：US08294500B1
公开(公告)日：2012-10-23
申请号：US12621493
申请日：2009-11-18
申请人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang , Van Ton-That
发明人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang , Van Ton-That
IPC分类号： H03H11/16
CPC分类号： G06G7/30
摘要： A phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.
摘要翻译：相位插值器电路包括耦合以形成差分对的第一和第二晶体管，负载电路，第一组开关电路，第二组开关电路和电流源。第一组开关电路耦合在第一晶体管和负载电路之间。第二组开关电路耦合在第二晶体管和负载电路之间。电流源为差分对提供电流。

2. 发明授权

US08619931B1 Multi-purpose phase-locked loop for low cost transceiver 有权
标题翻译：用于低成本收发器的多功能锁相环
公开(公告)号：US08619931B1
公开(公告)日：2013-12-31
申请号：US12622152
申请日：2009-11-19
申请人： Tien Duc Pham , Sergey Shumarayev , Tim Tri Hoang , Thungoc M. Tran , Vinh Van Ho , Leon Zheng
发明人： Tien Duc Pham , Sergey Shumarayev , Tim Tri Hoang , Thungoc M. Tran , Vinh Van Ho , Leon Zheng
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H04L7/002
摘要： Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.
摘要翻译：提供了具有能够在没有专用锁相环电路的情况下能够进行高速（例如，1Gbps）操作的收发器的集成电路。一个这样的集成电路设备可以包括能够发送和接收大约1Gbps或更大的串行信号的一个或多个收发器，以及能够向一个或多个收发器提供多相时钟信号的多用途锁相环。

3. 发明授权

US07994837B1 Techniques for phase interpolation 有权
标题翻译：相位插值技术
公开(公告)号：US07994837B1
公开(公告)日：2011-08-09
申请号：US12537634
申请日：2009-08-07
申请人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang
发明人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang
IPC分类号： H03H11/16
CPC分类号： H03H11/22
摘要： A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between the second transistor and the second load circuit, a current source circuit, and a third switch circuit coupled between the differential pair and the current source circuit. A phase interpolator circuit can include three differential pairs of transistors. Six periodic input signals having six different phases are concurrently provided to control inputs of transistors in the three differential pairs of transistors. The phase interpolator circuit generates a selected phase in an output signal in response to four of the periodic input signals.
摘要翻译：相位插值器电路可以包括耦合以形成差分对的第一和第二晶体管，第一和第二负载电路，耦合在第一晶体管和第一负载电路之间的第一开关电路，耦合在第二晶体管和第二负载电路之间的第二开关电路负载电路，电流源电路和耦合在差分对和电流源电路之间的第三开关电路。相位内插器电路可以包括三个差分对的晶体管。具有六个不同相位的六个周期性输入信号被同时提供以控制三个差分对晶体管中的晶体管的输入。相位插值器电路响应于四个周期性输入信号而在输出信号中产生所选择的相位。

4. 发明授权

US08228102B1 Phase-locked loop architecture and clock distribution system 有权
标题翻译：锁相环架构和时钟分配系统
公开(公告)号：US08228102B1
公开(公告)日：2012-07-24
申请号：US12717062
申请日：2010-03-03
申请人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
发明人： Tien Duc Pham , Sergey Shumarayev , Richard G. Cliff , Tim Tri Hoang , Weiqi Ding , Sriram Narayan , Thungoc M. Tran , Kumara Tharmalingam
IPC分类号： H03L7/06
CPC分类号： H03L7/23 , G06F1/10 , H03L7/0807 , H03L7/183 , H03L7/197 , H03L7/1974 , H04L7/0331
摘要： One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，该集成电路包括集成电路的第一侧上的第一条锁相环（PLL）电路，以及集成电路的第二侧的第二条PLL电路，该第二条与第一条侧。可以通过对集成电路进行编程来配置第一和第二条带中的PLL电路。另一实施例涉及包括多个锁相环（PLL）电路和与多个PLL电路相邻的多个物理介质连接（PMA）三元组模块的集成电路。每个PMA三元组模块包括第一，第二和第三通道。第一和第三通道被布置为用作接收通道，并且第二通道被布置为可配置为接收通道或时钟倍增单元。还公开了其它实施例和特征。

5. 发明授权

US07893726B1 Leakage compensation and improved setup/hold time in a dynamic flip-flop 有权
标题翻译：在动态触发器中泄漏补偿和改进的设置/保持时间
公开(公告)号：US07893726B1
公开(公告)日：2011-02-22
申请号：US11782443
申请日：2007-07-24
申请人： Vinh Van Ho , Tim Tri Hoang
发明人： Vinh Van Ho , Tim Tri Hoang
IPC分类号： G01R19/00
CPC分类号： G11C7/065 , G11C11/412 , H03K3/012 , H03K3/356139
摘要： A dynamic flip-flop includes first and second input stages forming a differential input stage adapted to receive differential data. The flip-flop is reset in response to a reset signal. To ensure proper operation, a transistor disposed between the first and second input stages is always maintained active to provide a conduction path between the ground terminal and the nodes that may be charged from the supply voltage. To improve the setup and hold time of the flip-flop, the clock signal is applied to a first transistor disposed in the first input stage and a second transistor disposed in the second input stage.
摘要翻译：动态触发器包括形成适于接收差分数据的差分输入级的第一和第二输入级。触发器响应于复位信号被复位。为了确保正常操作，设置在第一和第二输入级之间的晶体管总是保持有效，以在接地端子和节点之间提供可以从电源电压充电的导电路径。为了改善触发器的设置和保持时间，时钟信号被施加到设置在第一输入级中的第一晶体管和设置在第二输入级中的第二晶体管。

6. 发明授权

US08049532B1 Level shifter circuit with a thin gate oxide transistor 有权
标题翻译：具有薄栅极氧化物晶体管的电平移位电路
公开(公告)号：US08049532B1
公开(公告)日：2011-11-01
申请号：US12823596
申请日：2010-06-25
申请人： Simardeep Maangat , Vinh Van Ho , Tim Tri Hoang
发明人： Simardeep Maangat , Vinh Van Ho , Tim Tri Hoang
IPC分类号： H03K19/0175 , H03L5/00
CPC分类号： H03L7/085 , H03K19/017509 , H03L7/087
摘要： A level shifting circuit with a thin gate transistor connected to the input of the output stage is presented. The level shifting circuit has an input stage that receives an input that is at first voltage. A transistor with a thin gate oxide has one terminal connected to the input stage and another terminal coupled to an input of the output stage. The output stage of the level shifting circuit is implemented with thick gate oxide transistors.
摘要翻译：提出了一种具有连接到输出级的输入端的薄栅极晶体管的电平移动电路。电平移位电路具有接收处于第一电压的输入的输入级。具有薄栅极氧化物的晶体管具有连接到输入级的一个端子和耦合到输出级的输入的另一个端子。电平移位电路的输出级由厚栅极氧化物晶体管实现。

7. 发明授权

US10110328B2 Apparatus and methods for calibrating analog circuitry in an integrated circuit 有权
公开(公告)号：US10110328B2
公开(公告)日：2018-10-23
申请号：US13446555
申请日：2012-04-13
申请人： Neville Carvalho , Tim Tri Hoang , Sergey Shumarayev
发明人： Neville Carvalho , Tim Tri Hoang , Sergey Shumarayev
IPC分类号： G01R35/00 , H04B17/21 , H04B17/11 , G12B13/00
摘要： The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

8. 发明授权

US09559881B2 Transceiver system with reduced latency uncertainty 有权
标题翻译：收发器系统具有降低的延迟不确定性
公开(公告)号：US09559881B2
公开(公告)日：2017-01-31
申请号：US12283652
申请日：2008-09-15
申请人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
发明人： Neville Carvalho , Allan Thomas Davidson , Andy Turudic , Bruce B. Pedersen , David W. Mendel , Kalyan Kankipati , Michael Menghui Zheng , Sergey Shumarayev , Seungmyon Park , Tim Tri Hoang , Kumara Tharmalingam
IPC分类号： H04L7/00 , H04B1/38 , H04L25/14
CPC分类号： H04L25/14
摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.
摘要翻译：描述了具有降低的等待时间不确定性的收发机系统。在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

9. 发明授权

US08976804B1 Power supply filtering for programmable logic device having heterogeneous serial interface architecture 有权
标题翻译：具有异构串行接口架构的可编程逻辑器件的电源滤波
公开(公告)号：US08976804B1
公开(公告)日：2015-03-10
申请号：US13041764
申请日：2011-03-07
申请人： Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04L12/66
CPC分类号： H03K19/17744
摘要： In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.
摘要翻译：在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

10. 发明授权

US08653853B1 Differential interfaces for power domain crossings 有权
标题翻译：电源交叉口的差分接口
公开(公告)号：US08653853B1
公开(公告)日：2014-02-18
申请号：US11618828
申请日：2006-12-31
申请人： Sergey Shumarayev , Tim Tri Hoang , Lawrence David Smith
发明人： Sergey Shumarayev , Tim Tri Hoang , Lawrence David Smith
IPC分类号： H03K19/0175
CPC分类号： H03K19/0175 , G11C7/10 , G11C7/1057 , G11C7/1084 , H03K19/17744 , H03K19/17784 , H03K19/17788
摘要： Techniques are provided for transmitting signals through a differential interface between circuits in different power supply domains. A driver circuit in a first power supply domain converts single-ended signals into differential signals. The driver circuit then transmits the differential signals to a receiver circuit in a second power supply domain. The receiver circuit converts the differential signals back into single-ended signals for transmission to circuit elements in the second power supply domain. The differential interface reduces the transmission of noise between circuit elements in the first power supply domain and circuit elements in the second power supply domain.
摘要翻译：提供了用于通过不同电源域中的电路之间的差分接口传输信号的技术。第一电源域中的驱动电路将单端信号转换成差分信号。然后，驱动器电路将差分信号发送到第二电源域中的接收器电路。接收器电路将差分信号转换回单端信号以传输到第二电源域中的电路元件。差分接口减少了第一电源域中的电路元件与第二电源域中的电路元件之间的噪声传输。

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