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1. 发明申请

US20080244267A1 Local and remote access control of a resource 审中-公开
标题翻译：资源的本地和远程访问控制
公开(公告)号：US20080244267A1
公开(公告)日：2008-10-02
申请号：US11731433
申请日：2007-03-30
申请人： Vincent J. Zimmer , Burges M. Karkaria , Rahul Khanna , Yufu Li
发明人： Vincent J. Zimmer , Burges M. Karkaria , Rahul Khanna , Yufu Li
IPC分类号： H04L9/32
CPC分类号： G06F21/572
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for local and remote access to a resource. In some embodiments, an integrated circuit includes a configurable hardware resource. In addition, the integrated circuit may also include access control logic to authenticate agents that attempt to configure the resource. In some embodiments, the agents may be in-band or out-of-band agents. Other embodiments are described and claimed.
摘要翻译：本发明的实施例通常涉及用于本地和远程访问资源的系统，方法和装置。在一些实施例中，集成电路包括可配置的硬件资源。此外，集成电路还可以包括访问控制逻辑以验证尝试配置资源的代理。在一些实施例中，代理可以是带内或带外代理。描述和要求保护其他实施例。

2. 发明申请

US20080162873A1 Heterogeneous multiprocessing 审中-公开
标题翻译：异构多处理
公开(公告)号：US20080162873A1
公开(公告)日：2008-07-03
申请号：US11647501
申请日：2006-12-28
申请人： Vincent J. Zimmer , Yufu Li , Michael A. Rothman , Burges M. Karkaria
发明人： Vincent J. Zimmer , Yufu Li , Michael A. Rothman , Burges M. Karkaria
IPC分类号： G06F15/76
CPC分类号： G06F9/4405 , G06F15/17337
摘要： In some embodiments, the invention involves a system and method to provide maximal boot-time parallelism for future multi-core, multi-node, and many-core systems. In an embodiment, the security (SEC), pre-EFI initialization (PEI), and then driver execution environment (DXE) phases are executed in parallel on multiple compute nodes (sockets) of a platform. Once the SEC/PEI/DXE phases are executed on all compute nodes having a processor, the boot device select (BDS) phase completes the boot by merging or partitioning the compute nodes based on a platform policy. Partitioned compute nodes each run their own instance of EFI. A common memory map may be generated prior to operating system (OS) launch when compute nodes are to be merged. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明涉及为将来的多核，多节点和多核系统提供最大引导时间并行性的系统和方法。在一个实施例中，在平台的多个计算节点（套接字）上并行执行安全性（SEC），预EFI初始化（PEI）以及随后的驱动器执行环境（DXE）阶段。一旦在具有处理器的所有计算节点上执行SEC / PEI / DXE阶段，引导设备选择（BDS）阶段通过基于平台策略合并或划分计算节点来完成引导。分区计算节点每个运行自己的EFI实例。在计算节点要合并时，可能会在操作系统（OS）启动之前生成公共存储器映射。描述和要求保护其他实施例。

3. 发明申请

US20090083528A1 SYSTEM INFORMATION SYNCHRONIZATION IN A LINKS-BASED MULTI-PROCESSOR SYSTEM 有权
标题翻译：基于链路的多处理器系统中的系统信息同步
公开(公告)号：US20090083528A1
公开(公告)日：2009-03-26
申请号：US11859640
申请日：2007-09-21
申请人： Yufu Li , XiaoHua Cai , Rahul Khanna , Murugasamy Nachimuthu , Vincent J. Zimmer
发明人： Yufu Li , XiaoHua Cai , Rahul Khanna , Murugasamy Nachimuthu , Vincent J. Zimmer
IPC分类号： G06F15/76 , G06F15/167 , G06F9/02 , G06F15/177
CPC分类号： G06F15/177 , G06F9/4405
摘要： Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during system boot in a links-based multi-processor system. Some embodiments synchronize data block by block through memory rather than piece by piece through registers by allowing a System Bootstrap Processor (“SBSP”) to directly access synchronization data in local memory of each of one or more Application Processors. These and other embodiments are described in greater detail below.
摘要翻译：本文描述的各种实施例包括在基于链路的多处理器系统中的系统引导期间在处理器之间同步系统信息的系统，方法，固件和软件中的一个或多个。一些实施例通过允许系统引导处理器（“SBSP”）直接访问一个或多个应用处理器中的每一个的本地存储器中的同步数据，通过存储器而不是通过寄存器逐块同步数据。下面更详细地描述这些和其它实施例。

4. 发明授权

US07818560B2 System information synchronization in a links-based multi-processor system 有权
标题翻译：基于链路的多处理器系统中的系统信息同步
公开(公告)号：US07818560B2
公开(公告)日：2010-10-19
申请号：US11859640
申请日：2007-09-21
申请人： Yufu Li , XiaoHua Cai , Rahul Khanna , Murugasamy Nachimuthu , Vincent J. Zimmer
发明人： Yufu Li , XiaoHua Cai , Rahul Khanna , Murugasamy Nachimuthu , Vincent J. Zimmer
IPC分类号： G06F15/177
CPC分类号： G06F15/177 , G06F9/4405
摘要： Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during system boot in a links-based multi-processor system. Some embodiments synchronize data block by block through memory rather than piece by piece through registers by allowing a System Bootstrap Processor (“SBSP”) to directly access synchronization data in local memory of each of one or more Application Processors. These and other embodiments are described in greater detail below.
摘要翻译：本文描述的各种实施例包括在基于链路的多处理器系统中的系统引导期间在处理器之间同步系统信息的系统，方法，固件和软件中的一个或多个。一些实施例通过允许系统引导处理器（“SBSP”）直接访问一个或多个应用处理器中的每一个的本地存储器中的同步数据，通过存储器而不是通过寄存器逐块同步数据。下面更详细地描述这些和其它实施例。

5. 发明授权

US07856551B2 Dynamically discovering a system topology 有权
标题翻译：动态发现系统拓扑
公开(公告)号：US07856551B2
公开(公告)日：2010-12-21
申请号：US11810434
申请日：2007-06-05
申请人： Xiaohua Cai , Yufu Li , Murugasamy Nachimuthu , Rahul Khanna , Koo Heng Daniel AW , Wenson Lin
发明人： Xiaohua Cai , Yufu Li , Murugasamy Nachimuthu , Rahul Khanna , Koo Heng Daniel AW , Wenson Lin
IPC分类号： G06F9/00
CPC分类号： G06F15/17337 , G06F15/177
摘要： In one embodiment, the present invention includes a method for dynamically discovering a topology of a system having a plurality of point-to-point (PTP) links via a routine that communicates a link exchanged parameter with at least one component coupled to a system bootstrap processor (SBSP), sets a minimal set of routing infrastructure information based on the communication, and determines presence of a neighboring component to a target component based on a communication from the SBSP to the target component using the minimal set of routing infrastructure information. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于动态发现具有多个点对点（PTP）链路的系统的拓扑的方法，所述系统经由将链路交换的参数与耦合到系统引导的至少一个组件进行通信的例程处理器（SBSP）基于通信设置最小的路由基础设施信息集合，并且基于使用最小路由基础设施信息集从SBSP到目标组件的通信来确定邻近组件到目标组件的存在。描述和要求保护其他实施例。

6. 发明申请

US20080162982A1 METHODS AND APPARATUS TO CHANGE A CONFIGURATION OF A PROCESSOR SYSTEM 失效
标题翻译：改变处理器系统配置的方法和设备
公开(公告)号：US20080162982A1
公开(公告)日：2008-07-03
申请号：US11618422
申请日：2006-12-29
申请人： Yufu Li , Jian Tang , XiaoHua Cai , Murugasamy Nachimuthu , Rahul Khanna
发明人： Yufu Li , Jian Tang , XiaoHua Cai , Murugasamy Nachimuthu , Rahul Khanna
IPC分类号： G06F11/00
CPC分类号： G06F9/4812 , G06F9/5061
摘要： Methods and apparatus to change a configuration of a processor system are disclosed. An example disclosed method calculates system configuration data during a non-quiesce state of a processing system, stores information based on the calculated system configuration data in a data buffer during the non-quiesce state of the processing system, and extracts information from the data buffer to update the configuration of the processing system while the processing system is in a quiesce state.
摘要翻译：公开了改变处理器系统的配置的方法和装置。一个示例公开的方法在处理系统的非静默状态期间计算系统配置数据，在处理系统的非静止状态期间将基于所计算的系统配置数据的信息存储在数据缓冲器中，并且从数据缓冲器中提取信息在处理系统处于静止状态时更新处理系统的配置。

7. 发明授权

US07941810B2 Extensible and flexible firmware architecture for reliability, availability, serviceability features 有权
标题翻译：可扩展和灵活的固件架构，可靠性，可用性，可维护性功能
公开(公告)号：US07941810B2
公开(公告)日：2011-05-10
申请号：US11648419
申请日：2006-12-28
申请人： Rahul Khanna , Jian Tang , Yufu Li
发明人： Rahul Khanna , Jian Tang , Yufu Li
IPC分类号： G06F9/54 , G06F9/44
CPC分类号： G06F11/004 , G06F11/0709 , G06F11/0793
摘要： Improved reliability, availability, and serviceability (RAS) is provided by an extensible and flexible firmware architecture. The architecture provides management for events, where an event is a response to an imminent failure of or capacity change requirement applicable to a component of the system. In response to an event, control of a system is transferred from an operating system to the firmware manager. The manager identifies an action that is specified by the event. Based on the action, the firmware manager selects a firmware handler from a plurality of firmware handlers. The firmware manager dispatches the selected firmware handler to perform the specified action. The firmware manager and the dispatched firmware handler exchange system-independent information regarding the event. The firmware manager also manages time-slices for the performance of the specified action by the dispatched firmware handler.
摘要翻译：通过可扩展且灵活的固件架构提供可靠性，可用性和可维护性（RAS）的提高。该架构为事件提供管理，其中事件是对应用于系统组件的即将发生的故障或容量变化要求的响应。响应于事件，将系统的控制从操作系统传送到固件管理器。经理识别事件指定的动作。基于该动作，固件管理器从多个固件处理器中选择固件处理程序。固件管理器调度所选的固件处理程序以执行指定的操作。固件管理器和发送的固件处理程序交换与事件有关的系统无关信息。固件管理器还管理由分派的固件处理程序执行指定操作的时间片。

8. 发明授权

US07640453B2 Methods and apparatus to change a configuration of a processor system 失效
标题翻译：改变处理器系统配置的方法和装置
公开(公告)号：US07640453B2
公开(公告)日：2009-12-29
申请号：US11618422
申请日：2006-12-29
申请人： Yufu Li , Jian Tang , XiaoHua Cai , Murugasamy Nachimuthu , Rahul Khanna
发明人： Yufu Li , Jian Tang , XiaoHua Cai , Murugasamy Nachimuthu , Rahul Khanna
IPC分类号： G06F11/00
CPC分类号： G06F9/4812 , G06F9/5061
摘要： Methods and apparatus to change a configuration of a processor system are disclosed. An example disclosed method calculates system configuration data during a non-quiesce state of a processing system, stores information based on the calculated system configuration data in a data buffer during the non-quiesce state of the processing system, and extracts information from the data buffer to update the configuration of the processing system while the processing system is in a quiesce state.
摘要翻译：公开了改变处理器系统的配置的方法和装置。一个示例公开的方法在处理系统的非静默状态期间计算系统配置数据，在处理系统的非静止状态期间将基于所计算的系统配置数据的信息存储在数据缓冲器中，并且从数据缓冲器中提取信息在处理系统处于静止状态时更新处理系统的配置。

9. 发明申请

US20080163256A1 Extensible and flexible firmware architecture for reliability, availability, serviceability features 有权
标题翻译：可扩展和灵活的固件架构，可靠性，可用性，可维护性功能
公开(公告)号：US20080163256A1
公开(公告)日：2008-07-03
申请号：US11648419
申请日：2006-12-28
申请人： Rahul Khanna , Jian Tang , Yufu Li
发明人： Rahul Khanna , Jian Tang , Yufu Li
IPC分类号： G06F9/44
CPC分类号： G06F11/004 , G06F11/0709 , G06F11/0793
摘要： Improved reliability, availability, and serviceability (RAS) is provided by an extensible and flexible firmware architecture. The architecture provides management for events, where an event is a response to an imminent failure of or capacity change requirement applicable to a component of the system. In response to an event, control of a system is transferred from an operating system to the firmware manager. The manager identifies an action that is specified by the event. Based on the action, the firmware manager selects a firmware handler from a plurality of firmware handlers. The firmware manager dispatches the selected firmware handler to perform the specified action. The firmware manager and the dispatched firmware handler exchange system-independent information regarding the event. The firmware manager also manages time-slices for the performance of the specified action by the dispatched firmware handler.
摘要翻译：通过可扩展且灵活的固件架构提供可靠性，可用性和可维护性（RAS）的提高。该架构为事件提供管理，其中事件是对应用于系统组件的即将发生的故障或容量变化要求的响应。响应于事件，将系统的控制从操作系统传送到固件管理器。经理识别事件指定的动作。基于该动作，固件管理器从多个固件处理器中选择固件处理程序。固件管理器调度所选的固件处理程序以执行指定的操作。固件管理器和发送的固件处理程序交换与事件有关的系统无关信息。固件管理器还管理由分派的固件处理程序执行指定操作的时间片。

10. 发明授权

US08977871B2 System and method for power management using a basic input output system 有权
标题翻译：使用基本输入输出系统进行电源管理的系统和方法
公开(公告)号：US08977871B2
公开(公告)日：2015-03-10
申请号：US13107133
申请日：2011-05-13
申请人： Di Tang , Vincent Zimmer , James Edwards , Rahul Khanna , Yufu Li , Abdul Bailey
发明人： Di Tang , Vincent Zimmer , James Edwards , Rahul Khanna , Yufu Li , Abdul Bailey
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3228 , G06F1/3243 , G06F9/4401 , G06F9/4418 , Y02D10/152 , Y02D10/44 , Y02D50/20
摘要： A system comprises a plurality of processor cores. The processor cores may comprise one or more application processor (AP) cores and a boot strap processor (BSP) core. A basic input/output system (BIOS) comprises an I/O device module to call a stall function in response to an I/O operation, a power management module that couples to the I/O device and a timer module that couples to the power management module. The power management module is to adjust a timer period of the timer module based on a stall delay of the stall function. The power management module may hook the stall function and compare the stall delay with a predetermined threshold and set the timer period to the stall delay in response to determining that the stall delay is longer. The power management module may put the BSP in a sleep mode during the timer period to save power.
摘要翻译：一种系统包括多个处理器核。处理器核心可以包括一个或多个应用处理器（AP）核心和引导带处理器（BSP）核心。基本输入/输出系统（BIOS）包括响应于I / O操作来调用失速功能的I / O设备模块，耦合到I / O设备的电源管理模块和耦合到I / O设备的定时器模块电源管理模块电源管理模块是根据失速功能的停止延迟来调整定时器模块的定时器周期。功率管理模块可以挂起失速功能并将失速延迟与预定阈值进行比较，并响应于确定失速延迟更长而将定时器周期设置为失速延迟。电源管理模块可以在定时器周期内将BSP置于睡眠模式，以节省电力。

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