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1. 发明申请

US20100123140A1 SiC SUBSTRATES, SEMICONDUCTOR DEVICES BASED UPON THE SAME AND METHODS FOR THEIR MANUFACTURE 审中-公开
标题翻译： SiC基板，基于其的半导体器件及其制造方法
公开(公告)号：US20100123140A1
公开(公告)日：2010-05-20
申请号：US12275067
申请日：2008-11-20
申请人： Victor Lienkong Lou , Kevin Sean Matocha , Aveek Chatterjee , Vinayak Tilak , Stephen Arthur , Zachary Stum
发明人： Victor Lienkong Lou , Kevin Sean Matocha , Aveek Chatterjee , Vinayak Tilak , Stephen Arthur , Zachary Stum
IPC分类号： H01L21/30 , H01L29/24
CPC分类号： H01L21/049
摘要： The present invention generally relates to a method for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, the present invention provides a method for the manufacture of a semiconductor device based upon a silicon carbide substrate and comprising an oxide layer comprising incorporating at least one additive into the atomic structure of the oxide layer. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 60 cm2/Vs.
摘要翻译：本发明一般涉及一种在基于碳化硅（SiC）衬底的半导体器件中提高反层迁移率和提供低缺陷密度的方法。更具体地说，本发明提供一种制造基于碳化硅衬底的半导体器件的方法，该方法包括将至少一种添加剂结合到氧化物层的原子结构中的氧化物层。预期基于根据本方法处理的衬底的诸如MOSFET的半导体器件具有至少约60cm 2 / Vs的反转层迁移率。

2. 发明授权

US08217398B2 Method for the formation of a gate oxide on a SiC substrate and SiC substrates and devices prepared thereby 有权
标题翻译：在SiC衬底和SiC衬底上形成栅极氧化物的方法以及由此制备的器件
公开(公告)号：US08217398B2
公开(公告)日：2012-07-10
申请号：US12251866
申请日：2008-10-15
申请人： Victor Lienkong Lou , Kevin Sean Matocha , Gregory Thomas Dunne
发明人： Victor Lienkong Lou , Kevin Sean Matocha , Gregory Thomas Dunne
IPC分类号： H01L29/15 , H01L21/31
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/049 , H01L21/31658 , H01L29/66068 , H01L29/78
摘要： Methods are provided for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, embodiments of the present method provide for the formation of a gate oxide on a silicon carbide substrate comprising oxidizing the substrate with a gaseous mixture comprising oxygen at a temperature of at least about 1300° C. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 12 cm2/Vs.
摘要翻译：提供了用于在基于碳化硅（SiC）衬底的半导体器件中改善反型层迁移率和提供低缺陷密度的方法。更具体地，本方法的实施例提供了在碳化硅衬底上形成栅极氧化物，包括在至少约1300℃的温度下，用包含氧的气体混合物氧化衬底。基于MOSFET的半导体器件在根据本方法处理的基底上，期望具有至少约12cm 2 / Vs的反转层迁移率。

3. 发明申请

US20100090227A1 METHOD FOR THE FORMATION OF A GATE OXIDE ON A SIC SUBSTRATE AND SIC SUBSTRATES AND DEVICES PREPARED THEREBY 有权
标题翻译：在SIC基板和SIC基板上形成栅极氧化物的方法及其制备的器件
公开(公告)号：US20100090227A1
公开(公告)日：2010-04-15
申请号：US12251866
申请日：2008-10-15
申请人： Victor Lienkong Lou , Kevin Sean Matocha , Gregory Thomas Dunne
发明人： Victor Lienkong Lou , Kevin Sean Matocha , Gregory Thomas Dunne
IPC分类号： H01L29/15 , H01L21/31
CPC分类号： H01L29/7802 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/049 , H01L21/31658 , H01L29/66068 , H01L29/78
摘要： Methods are provided for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, embodiments of the present method provide for the formation of a gate oxide on a silicon carbide substrate comprising oxidizing the substrate with a gaseous mixture comprising oxygen at a temperature of at least about 1300° C. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 12 cm2/Vs.
摘要翻译：提供了用于在基于碳化硅（SiC）衬底的半导体器件中改善反型层迁移率和提供低缺陷密度的方法。更具体地，本方法的实施例提供了在碳化硅衬底上形成栅极氧化物，包括在至少约1300℃的温度下，用包含氧的气体混合物氧化衬底。基于MOSFET的半导体器件在根据本方法处理的基底上，期望具有至少约12cm 2 / Vs的反转层迁移率。

4. 发明申请

US20080146004A1 SILICON CARBIDE DEVICES AND METHOD OF MAKING 失效
标题翻译：碳化硅器件及其制造方法
公开(公告)号：US20080146004A1
公开(公告)日：2008-06-19
申请号：US11610199
申请日：2006-12-13
申请人： Kevin Sean Matocha , Vinayak Tilak , Stephen Daley Arthur , Zachary Matthew Stum
发明人： Kevin Sean Matocha , Vinayak Tilak , Stephen Daley Arthur , Zachary Matthew Stum
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/0465 , H01L29/66068
摘要： A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.
摘要翻译：公开了一种制造SiC MOSFET的方法。该方法包括在衬底上生长SiC外延层，平面化SiC外延层以提供平坦化的SiC外延层，以及形成与平坦化的外延层接触的栅极电介质层。

5. 发明授权

US07589360B2 Group III nitride semiconductor devices and methods of making 失效
标题翻译： III族氮化物半导体器件及其制造方法
公开(公告)号：US07589360B2
公开(公告)日：2009-09-15
申请号：US11594473
申请日：2006-11-08
申请人： Kevin Sean Matocha , Vinayak Tilak
发明人： Kevin Sean Matocha , Vinayak Tilak
IPC分类号： H01L29/06
CPC分类号： H01L29/045 , H01L29/2003 , H01L29/94
摘要： A device having an electrode-insulator layer-group III nitride layer structure, wherein an interface between the insulator layer and the group III nitride semiconductor layer lies along a non-polar plane of the group III nitride semiconductor layer is provided.
摘要翻译：提供了具有电极 - 绝缘体层III族氮化物层结构的器件，其中绝缘体层和III族氮化物半导体层之间的界面位于III族氮化物半导体层的非极性平面。

6. 发明申请

US20080121927A1 Group III nitride semiconductor devices and methods of making 失效
标题翻译： III族氮化物半导体器件及其制造方法
公开(公告)号：US20080121927A1
公开(公告)日：2008-05-29
申请号：US11594473
申请日：2006-11-08
申请人： Kevin Sean Matocha , Vinayak Tilak
发明人： Kevin Sean Matocha , Vinayak Tilak
IPC分类号： H01L29/20 , H01L21/336
CPC分类号： H01L29/045 , H01L29/2003 , H01L29/94
摘要： A device having an electrode-insulator layer-group III nitride layer structure, wherein an interface between the insulator layer and the group III nitride semiconductor layer lies along a non-polar plane of the group III nitride semiconductor layer is provided.
摘要翻译：提供了具有电极 - 绝缘体层III族氮化物层结构的器件，其中绝缘体层和III族氮化物半导体层之间的界面位于III族氮化物半导体层的非极性平面。

7. 发明申请

US20120171824A1 HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD 有权
标题翻译：异体结构设备及相关方法
公开(公告)号：US20120171824A1
公开(公告)日：2012-07-05
申请号：US13418566
申请日：2012-03-13
申请人： Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
发明人： Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
IPC分类号： H01L21/335
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/207
摘要： A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.
摘要翻译：提供了一种制造异质结构器件的方法，其包括将离子注入到多层结构的表面的一部分中。碘离子注入第一区域和第二区域之间以形成第三区域。电荷从第三区域中的二维电子气（2DEG）通道中消耗，以形成从第一区域到第二区域的可逆的非导电通路。在向靠近第三区域的栅电极施加电压电位时，允许电流从第一区域流到第二区域。

8. 发明申请

US20090140293A1 HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD 审中-公开
标题翻译：异体结构设备及相关方法
公开(公告)号：US20090140293A1
公开(公告)日：2009-06-04
申请号：US11946959
申请日：2007-11-29
申请人： Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Vinayak Tilak , Siddharth Rajan , Ho-Young Cha
发明人： Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Vinayak Tilak , Siddharth Rajan , Ho-Young Cha
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/2003
摘要： A heterostructure device or article includes a carrier transport layer, a back channel layer and a barrier layer. The carrier transport layer has a first surface and a second surface opposing to the first surface. The back channel layer is secured to the first surface of the carrier transport layer and the barrier layer is secured to the second surface of the carrier transport layer. Each of the carrier transport layer, the back channel layer and the barrier layer comprises an aluminum gallium nitride alloy. The article further includes a 2D electron gas at an interface of the second surface of the carrier transport layer and a surface of the barrier layer. The 2D electron gas is defined by a bandgap differential at an interface, which allows for electron mobility. A system includes a heterostructure field effect transistor that includes the article.
摘要翻译：异质结构器件或制品包括载流子传输层，背沟道层和阻挡层。载流子传输层具有与第一表面相对的第一表面和第二表面。背沟道层被固定到载流子传输层的第一表面，并且阻挡层固定到载流子传输层的第二表面。载流子传输层，背沟道层和阻挡层中的每一个包括氮化镓铝合金。该制品还包括在载流子传输层的第二表面和势垒层的表面的界面处的2D电子气体。 2D电子气体由界面处的带隙差分限定，这允许电子迁移率。一种系统包括包括该物品的异质结构场效应晶体管。

9. 发明授权

US07521732B2 Vertical heterostructure field effect transistor and associated method 有权
标题翻译：垂直异质结场场效应晶体管及相关方法
公开(公告)号：US07521732B2
公开(公告)日：2009-04-21
申请号：US11283451
申请日：2005-11-18
申请人： Kevin Sean Matocha , Vinayak Tilak
发明人： Kevin Sean Matocha , Vinayak Tilak
IPC分类号： H01L29/20
CPC分类号： H01L29/7787 , H01L29/045 , H01L29/2003 , H01L29/42316 , H01L29/4236 , H01L29/7788 , H01L29/7789
摘要： A vertical heterostructure field effect transistor including a first layer having a first material, and the first material having a hexagonal crystal lattice structure defining a first bandgap and one or more non-polar planes is provided. The transistor further includes a second layer that is adjacent to the first layer having a second material. Further, the second layer has a first surface and a second surface, and a portion of the second layer first surface is coupled to the surface of the first layer to form a two dimensional charge gas and to define a first region. The second material may have a second bandgap that is different than the first bandgap. Furthermore, the transistor may include a conductive layer that is disposed in the trench and is interposed between the first region and a second region that is not in electrical communication with the first region if no electrical potential is applied to the conductive layer, and an electrical potential applied to the conductive layer allows electrical communication from the first region to the second region.
摘要翻译：提供了一种垂直异质结场效应晶体管，其包括具有第一材料的第一层，并且提供了具有限定第一带隙和一个或多个非极性平面的六方晶格结构的第一材料。所述晶体管还包括与所述第一层相邻的第二层，所述第二层具有第二材料。此外，第二层具有第一表面和第二表面，并且第二层第一表面的一部分耦合到第一层的表面以形成二维充电气体并限定第一区域。第二材料可以具有与第一带隙不同的第二带隙。此外，晶体管可以包括设置在沟槽中并且如果没有电位施加到导电层的第一区域和不与第一区域电连通的第二区域的导电层，施加到导电层的电位允许从第一区域到第二区域的电连通。

10. 发明授权

US08159002B2 Heterostructure device and associated method 有权
标题翻译：异质结构装置及相关方法
公开(公告)号：US08159002B2
公开(公告)日：2012-04-17
申请号：US11961532
申请日：2007-12-20
申请人： Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
发明人： Vinayak Tilak , Alexei Vertiatchikh , Kevin Sean Matocha , Peter Micah Sandvik , Siddharth Rajan
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/207
摘要： A heterostructure device includes a semiconductor multi-layer structure that has a first region, a second region and a third region. The first region is coupled to a source electrode and the second region is coupled to a drain electrode. The third region is disposed between the first region and the second region. The third region provides a switchable electrically conductive pathway from the source electrode to the drain electrode. The third region includes iodine ions. A system includes a heterostructure field effect transistor that includes the device.
摘要翻译：异质结构器件包括具有第一区域，第二区域和第三区域的半导体多层结构。第一区域耦合到源电极，第二区域耦合到漏电极。第三区域设置在第一区域和第二区域之间。第三区域提供从源电极到漏电极的可切换导电路径。第三区域包括碘离子。一种系统包括包括该器件的异质结构场效应晶体管。

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