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1. 发明申请

US20050006347A1 Hard mask removal 有权
标题翻译：硬面膜去除
公开(公告)号：US20050006347A1
公开(公告)日：2005-01-13
申请号：US10615558
申请日：2003-07-08
申请人： Venkatesh Gopinath , Arvind Kamath , Mohammad Mirabedini , Ming-Yi Lee , Brian Baylis
发明人： Venkatesh Gopinath , Arvind Kamath , Mohammad Mirabedini , Ming-Yi Lee , Brian Baylis
IPC分类号： H01L21/311 , C23F1/00
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.
摘要翻译：从形成在下层上的图案化层去除硬掩模层的方法，其中使用蚀刻剂去除硬掩模层，当底层在通常需要的时间长时间暴露于蚀刻剂时不利地蚀刻下面的层以去除硬掩模层，而不会有害地蚀刻下面的层。修改硬掩模层，使得蚀刻剂以比蚀刻剂蚀刻下层的蚀刻剂快得多的速率蚀刻硬掩模层。图案化硬掩模层。蚀刻图案层以暴露下层的部分。硬掩模层和下层的暴露部分用蚀刻剂蚀刻，其中蚀刻剂以比蚀刻剂蚀刻下层的速率快得多的速度蚀刻硬掩模层，这是因为硬的掩模层。

2. 发明授权

US06544829B1 Polysilicon gate salicidation 有权
标题翻译：多晶硅栅盐化
公开(公告)号：US06544829B1
公开(公告)日：2003-04-08
申请号：US10251016
申请日：2002-09-20
申请人： Venkatesh Gopinath , Mohammad Mirabedini , Charles E. May , Arvind Kamath
发明人： Venkatesh Gopinath , Mohammad Mirabedini , Charles E. May , Arvind Kamath
IPC分类号： H01L218238
CPC分类号： H01L21/823835 , H01L21/823814 , H01L21/823878
摘要： A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer, and a well region disposed between isolation structures. Portions of the hard mask material are removed to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, leaving exposed second portions of the unpatterned polysilicon layer and the gate oxide layer. The integrated circuit substrate is exposed to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, which defines source drain regions in the well region. The exposed second portions of the unpatterned polysilicon layer are removed to define polysilicon gate electrode precursors under the gate electrode masks. The gate electrode masks are removed from the polysilicon gate electrode precursors, and a metal layer is deposited over the polysilicon gate electrode precursors and the source drain regions. The integrated circuit substrate is annealed to substantially completely consume the polysilicon gate electrode precursors and form silicide gate electrodes from the polysilicon gate electrode precursors and the overlying metal layer, by which silicide contacts in the source drain regions are also formed.
摘要翻译：一种在CMOS工艺流程中制造基本上完全硅化的多晶硅栅电极的方法。在集成电路基板上形成硬掩模材料，其中集成电路基板包括覆盖在栅极氧化物层上的未图案化的多晶硅层和设置在隔离结构之间的阱区域。去除硬掩模材料的部分以限定覆盖未图案化多晶硅层和栅极氧化物层的第一部分的栅电极掩模，留下未图案化的多晶硅层和栅极氧化物层的暴露的第二部分。集成电路基板暴露于穿过栅极氧化物层的第二部分但不穿过限定阱区中的源极漏极区域的栅极电极掩模之下的栅极氧化物层的第一部分的掺杂剂。去除未图案化的多晶硅层的暴露的第二部分以在栅极电极掩模下限定多晶硅栅电极前体。栅极电极掩模从多晶硅栅电极前驱体去除，并且金属层沉积在多晶硅栅极电极前体和源极漏极区上。将集成电路基板退火以基本上完全消耗多晶硅栅极电极前体，并从多晶硅栅极电极前体和上覆金属层形成硅化物栅极电极，由此源极漏极区域中的硅化物接触也形成。

3. 发明授权

US06989331B2 Hard mask removal 有权
标题翻译：硬面膜去除
公开(公告)号：US06989331B2
公开(公告)日：2006-01-24
申请号：US10615558
申请日：2003-07-08
申请人： Venkatesh Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee , Brian A. Baylis
发明人： Venkatesh Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee , Brian A. Baylis
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.
摘要翻译：从形成在下层上的图案化层去除硬掩模层的方法，其中使用蚀刻剂去除硬掩模层，当底层在通常需要的时间长时间暴露于蚀刻剂时不利地蚀刻下面的层以去除硬掩模层，而不会有害地蚀刻下面的层。修改硬掩模层，使得蚀刻剂以比蚀刻剂蚀刻下层的蚀刻剂快得多的速率蚀刻硬掩模层。图案化硬掩模层。蚀刻图案层以暴露下层的部分。硬掩模层和下层的暴露部分用蚀刻剂蚀刻，其中蚀刻剂以比蚀刻剂蚀刻下层的速率快得多的速度蚀刻硬掩模层，这是因为硬的掩模层。

4. 发明授权

US06562729B2 Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit 有权
公开(公告)号：US06562729B2
公开(公告)日：2003-05-13
申请号：US10171700
申请日：2002-06-14
申请人： Arvind Kamath , Rajiv Patel , Mohammad Mirabedini
发明人： Arvind Kamath , Rajiv Patel , Mohammad Mirabedini
IPC分类号： H01L2131
CPC分类号： H01L21/823462
摘要： Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer. A slight, beneficial silicon dioxide interface is created between the silicon nitride and the silicon substrate as a result of oxidizing the new layer of silicon dioxide.

5. 发明授权

US06436845B1 Silicon nitride and silicon dioxide gate insulator transistors and method of forming same in a hybrid integrated circuit 有权
公开(公告)号：US06436845B1
公开(公告)日：2002-08-20
申请号：US09723516
申请日：2000-11-28
申请人： Arvind Kamath , Rajiv Patel , Mohammad Mirabedini
发明人： Arvind Kamath , Rajiv Patel , Mohammad Mirabedini
IPC分类号： H01L2131
CPC分类号： H01L21/823462
摘要： Silicon nitride gate insulators for digital transistors and silicon dioxide gate insulators for analog transistors of a hybrid integrated circuit (IC) are formed in a single integrated fabrication process. A first area of a silicon substrate of the IC is exposed while a second area is initially covered by a silicon dioxide layer. A layer of silicon nitride is formed on the exposed first area while the initial silicon dioxide layer inhibits the formation of silicon nitride on the second area. Thereafter the initial silicon dioxide layer is removed from the second area to allow a new silicon dioxide layer to be formed there from the exposed silicon substrate. The silicon dioxide layer shields against the adverse influences from silicon nitride formation and permits the initial silicon dioxide layer to be removed by etching. The silicon nitride layer shields against the adverse influences of oxidizing new silicon dioxide layer. A slight, beneficial silicon dioxide interface is created between the silicon nitride and the silicon substrate as a result of oxidizing the new layer of silicon dioxide.

6. 发明授权

US07413996B2 High k gate insulator removal 有权
标题翻译：高k栅绝缘子去除
公开(公告)号：US07413996B2
公开(公告)日：2008-08-19
申请号：US10413051
申请日：2003-04-14
申请人： Arvind Kamath , Wai Lo , Venkatesh Gopinath
发明人： Arvind Kamath , Wai Lo , Venkatesh Gopinath
IPC分类号： H01L21/00
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/31122 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an ion implanted species that causes lattice damage to the exposed portions of the high k layer. The lattice damaged exposed portions of the high k layer are etched to leave the high k gate insulation layer.
摘要翻译：在基板上的集成电路中形成高k栅极绝缘层的方法。将高k层沉积在衬底上，并用掩模图案以限定高k栅极绝缘层和高k层的暴露部分。高k层的暴露部分经受离子注入物质，其导致对高k层的暴露部分的晶格损伤。蚀刻高K层的晶格损坏的暴露部分以留下高k栅极绝缘层。

7. 发明授权

US06812158B1 Modular growth of multiple gate oxides 有权
标题翻译：多栅极氧化物的模块生长
公开(公告)号：US06812158B1
公开(公告)日：2004-11-02
申请号：US10335177
申请日：2002-12-31
申请人： Wen-Chin Yeh , Venkatesh Gopinath , Arvind Kamath
发明人： Wen-Chin Yeh , Venkatesh Gopinath , Arvind Kamath
IPC分类号： H01L2131
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31658 , H01L21/823462 , H01L21/823481 , Y10S438/981
摘要： Growth of multiple gate oxides. By implanting different sites of a wafer with different doses of an oxide growth retardant, the entire wafer can grow oxides of different thicknesses even after being exposed to the same oxidation environment. The process is modular insofar as the implantation of one site has no effect on rate of growth of other sites.
摘要翻译：多栅极氧化物的生长。通过用不同剂量的氧化物生长阻滞剂植入晶片的不同位置，即使在暴露于相同的氧化环境之后，整个晶片也可以生长不同厚度的氧化物。该过程是模块化的，因为一个位点的植入对其他位点的生长速率没有影响。

8. 发明授权

US07619294B1 Shallow trench isolation structure with low trench parasitic capacitance 失效
标题翻译：浅沟槽隔离结构具有低沟槽寄生电容
公开(公告)号：US07619294B1
公开(公告)日：2009-11-17
申请号：US11262173
申请日：2005-10-28
申请人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
发明人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译：提供了用于在集成电路基板上形成隔离结构的方法和组合物。首先，在集成电路基板中蚀刻沟槽。然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容要减少

9. 发明授权

US07001823B1 Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance 有权
标题翻译：制造具有低沟槽寄生电容的浅沟槽隔离结构的方法
公开(公告)号：US07001823B1
公开(公告)日：2006-02-21
申请号：US09991202
申请日：2001-11-14
申请人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
发明人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译：提供了用于在集成电路基板上形成隔离结构的方法和组合物。首先，在集成电路基板中蚀刻沟槽。然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容要减少

10. 发明授权

US08021955B1 Method characterizing materials for a trench isolation structure having low trench parasitic capacitance 有权
标题翻译：用于具有低沟槽寄生电容的沟槽隔离结构的方法表征材料
公开(公告)号：US08021955B1
公开(公告)日：2011-09-20
申请号：US12574426
申请日：2009-10-06
申请人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
发明人： Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.
摘要翻译：提供了用于在集成电路基板上形成多层隔离结构的方法和组合物。工艺可以包括为下电介质层选择下电介质材料，并选择用于上电介质层的上电介质材料。选择对应于下部和上部介电材料的厚度的一系列有效介电常数。下介电层和上电介质层中的每一个的厚度范围由可接受的介电常数的范围决定，使用表示与下部上部电介质层的材料的厚度对应的有效介电常数的信息，能够形成多层电介质层，层隔离结构。

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