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1. 发明申请

US20120181613A1 Methods for Forming Field Effect Transistor Devices With Protective Spacers 审中-公开
标题翻译：用保护隔离层形成场效应晶体管器件的方法
公开(公告)号：US20120181613A1
公开(公告)日：2012-07-19
申请号：US13009271
申请日：2011-01-19
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , Steven J. Holmes , Sivananda K. Kanakasabapathy
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , Steven J. Holmes , Sivananda K. Kanakasabapathy
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/66477 , H01L21/823418 , H01L21/823468 , H01L29/78
摘要： A method for forming a field effect transistor device includes forming a first gate stack and a second gate stack on a substrate, depositing a first photoresist material over the second gate stack and a portion of the substrate, implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack, depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material, removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region, removing the first photoresist material, and removing the first spacer.
摘要翻译：一种用于形成场效应晶体管器件的方法包括在衬底上形成第一栅极堆叠和第二栅极叠层，在第二栅极堆叠上沉积第一光致抗蚀剂材料和衬底的一部分，将衬底的暴露区域中的离子注入到限定与第一栅极堆叠相邻的第一源极区域和第一漏极区域，在第一源极区域，第一栅极堆叠层，第一漏极区域和第一光致抗蚀剂材料上沉积第一保护层，去除第一保护层以露出第一光致抗蚀剂材料并且限定设置在第一源极区域和第一漏极区域的一部分上的第一间隔物，去除第一光致抗蚀剂材料，以及移除第一间隔物。

2. 发明申请

US20120168931A1 CARBON NANOTUBE STRUCTURES FOR ENHANCEMENT OF THERMAL DISSIPATION FROM SEMICONDUCTOR MODULES 有权
标题翻译：用于增强半导体模块散热的碳纳米管结构
公开(公告)号：US20120168931A1
公开(公告)日：2012-07-05
申请号：US13418454
申请日：2012-03-13
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
IPC分类号： H01L23/36 , H01L21/50 , B82Y99/00 , B82Y40/00
CPC分类号： H01L23/373 , B82Y10/00 , B82Y40/00 , H01L21/6835 , H01L23/3157 , H01L23/433 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/81 , H01L24/94 , H01L29/0657 , H01L2221/6835 , H01L2221/68377 , H01L2224/0401 , H01L2224/05026 , H01L2224/05186 , H01L2224/05561 , H01L2224/05564 , H01L2224/05571 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/10135 , H01L2224/113 , H01L2224/11845 , H01L2224/13021 , H01L2224/13076 , H01L2224/131 , H01L2224/13147 , H01L2224/13184 , H01L2224/13187 , H01L2224/13193 , H01L2224/16221 , H01L2224/1703 , H01L2224/17515 , H01L2224/274 , H01L2224/73253 , H01L2224/81139 , H01L2224/81191 , H01L2224/81193 , H01L2224/81493 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/14 , H01L2924/04953 , H01L2224/05552
摘要： Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.
摘要翻译：公开了在后表面上具有碳纳米管（CNT）的保护簇的改进的半导体晶片结构的实施方案和形成改进的半导体晶片结构的方法。还公开了在后表面上具有暴露的CNT的半导体模块的实施例，用于与散热器一起提供增强的散热以及使用所公开的半导体晶片结构形成半导体模块的方法。

3. 发明授权

US08933559B2 Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules 有权
标题翻译：碳纳米管结构，用于增强半导体模块的散热
公开(公告)号：US08933559B2
公开(公告)日：2015-01-13
申请号：US13418454
申请日：2012-03-13
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
IPC分类号： H01L23/34 , H01L23/373 , B82Y10/00 , B82Y40/00 , H01L21/683 , H01L23/31 , H01L23/433 , H01L23/00 , H01L29/06
CPC分类号： H01L23/373 , B82Y10/00 , B82Y40/00 , H01L21/6835 , H01L23/3157 , H01L23/433 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/81 , H01L24/94 , H01L29/0657 , H01L2221/6835 , H01L2221/68377 , H01L2224/0401 , H01L2224/05026 , H01L2224/05186 , H01L2224/05561 , H01L2224/05564 , H01L2224/05571 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/10135 , H01L2224/113 , H01L2224/11845 , H01L2224/13021 , H01L2224/13076 , H01L2224/131 , H01L2224/13147 , H01L2224/13184 , H01L2224/13187 , H01L2224/13193 , H01L2224/16221 , H01L2224/1703 , H01L2224/17515 , H01L2224/274 , H01L2224/73253 , H01L2224/81139 , H01L2224/81191 , H01L2224/81193 , H01L2224/81493 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/14 , H01L2924/04953 , H01L2224/05552
摘要： Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.
摘要翻译：公开了在后表面上具有碳纳米管（CNT）的保护簇的改进的半导体晶片结构的实施方案和形成改进的半导体晶片结构的方法。还公开了在后表面上具有暴露的CNT的半导体模块的实施例，用于与散热器一起提供增强的散热以及使用所公开的半导体晶片结构形成半导体模块的方法。

4. 发明申请

US20100330756A1 INTEGRATED CIRCUIT STRUCTURE MANUFACTURING METHODS USING HARD MASK AND PHOTORESIST COMBINATION 审中-公开
标题翻译：使用硬掩模和光电组合的集成电路结构制造方法
公开(公告)号：US20100330756A1
公开(公告)日：2010-12-30
申请号：US12491270
申请日：2009-06-25
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , Steven J. Holmes
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , Steven J. Holmes
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of manufacturing an integrated circuit structure implants a first-type of channel implant in a first area of a substrate and implants a second-type of channel implant in a second area of the substrate. The method forms at least one first gate conductor above the first area of the substrate and forms at least one second gate conductor above the second area of the substrate. The method forms a hard mask over the first gate conductor, the second gate conductor, and the substrate. The hard mask comprises an oxide or a nitride and patterns an organic photoresist over the hard mask, to leave the organic photoresist on areas of the hard mask that are above the first area of the substrate. The method removes portions of the hard mask not protected by the organic photoresist to leave the hard mask on the first area of the substrate and not on the second area of the substrate. The method then removes the organic photoresist, implants impurities in the second area of the substrate to form source and drain regions adjacent the second gate conductor; and removes the hard mask using a wet etching process.
摘要翻译：一种制造集成电路结构的方法是将衬底的第一区域中的第一种沟道注入植入，并在衬底的第二区域中注入第二类沟道注入。该方法在衬底的第一区域之上形成至少一个第一栅极导体，并在衬底的第二区域上方形成至少一个第二栅极导体。该方法在第一栅极导体，第二栅极导体和衬底上形成硬掩模。硬掩模包括氧化物或氮化物，并且在硬掩模上形成有机光致抗蚀剂，以将有机光致抗蚀剂留在位于衬底的第一区域上方的硬掩模的区域上。该方法除去未被有机光致抗蚀剂保护的硬掩模的部分，以将硬掩模留在衬底的第一区域上，而不在衬底的第二区域上。该方法然后去除有机光致抗蚀剂，在衬底的第二区域内植入杂质以形成邻近第二栅极导体的源区和漏区; 并使用湿蚀刻工艺去除硬掩模。

5. 发明申请

US20090121343A1 CARBON NANOTUBE STRUCTURES FOR ENHANCEMENT OF THERMAL DISSIPATION FROM SEMICONDUCTOR MODULES 有权
标题翻译：用于增强半导体模块散热的碳纳米管结构
公开(公告)号：US20090121343A1
公开(公告)日：2009-05-14
申请号：US11939599
申请日：2007-11-14
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
IPC分类号： H01L21/50 , H01L23/34
CPC分类号： H01L23/373 , B82Y10/00 , B82Y40/00 , H01L21/6835 , H01L23/3157 , H01L23/433 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/81 , H01L24/94 , H01L29/0657 , H01L2221/6835 , H01L2221/68377 , H01L2224/0401 , H01L2224/05026 , H01L2224/05186 , H01L2224/05561 , H01L2224/05564 , H01L2224/05571 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/10135 , H01L2224/113 , H01L2224/11845 , H01L2224/13021 , H01L2224/13076 , H01L2224/131 , H01L2224/13147 , H01L2224/13184 , H01L2224/13187 , H01L2224/13193 , H01L2224/16221 , H01L2224/1703 , H01L2224/17515 , H01L2224/274 , H01L2224/73253 , H01L2224/81139 , H01L2224/81191 , H01L2224/81193 , H01L2224/81493 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/14 , H01L2924/04953 , H01L2224/05552
摘要： Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.
摘要翻译：公开了在后表面上具有碳纳米管（CNT）的保护簇的改进的半导体晶片结构的实施方案和形成改进的半导体晶片结构的方法。还公开了在后表面上具有暴露的CNT的半导体模块的实施例，用于与散热器一起提供增强的散热以及使用所公开的半导体晶片结构形成半导体模块的方法。

6. 发明申请

US20090032491A1 CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FORM DIELECTRIC LAYER 审中-公开
标题翻译：使用形成介质层的真实层形成的导电元件
公开(公告)号：US20090032491A1
公开(公告)日：2009-02-05
申请号：US11833301
申请日：2007-08-03
申请人： Veeraraghavan S. Basker , Steven J. Holmes , David V. Horak , Muthumanickam Sankarapandian
发明人： Veeraraghavan S. Basker , Steven J. Holmes , David V. Horak , Muthumanickam Sankarapandian
IPC分类号： H01B13/00 , B32B3/10
CPC分类号： H01L21/76808 , H01L21/76802 , H01L2221/1026 , H01L2221/1031 , Y10T428/24273
摘要： Methods of forming a conductive element for an integrated circuit (IC) chip and a related structure are disclosed. One embodiment of the method may include forming a first sacrificial layer having a pattern therein for a first dielectric layer to surround the conductive element; forming the first dielectric layer within the patterned first sacrificial layer; removing the patterned first sacrificial layer, leaving the first dielectric layer; and forming the conductive element in a space vacated by the patterned first sacrificial layer. The methods prevent damage caused to low dielectric constant dielectric layers during etching and stripping/cleaning processes.
摘要翻译：公开了形成用于集成电路（IC）芯片的导电元件和相关结构的方法。该方法的一个实施例可以包括形成其中具有图案的第一牺牲层用于第一介电层以围绕导电元件; 在所述图案化的第一牺牲层内形成所述第一介电层; 去除图案化的第一牺牲层，留下第一介电层; 以及在由图案化的第一牺牲层腾出的空间中形成导电元件。该方法防止在蚀刻和剥离/清洗过程中对低介电常数电介质层造成的损坏。

7. 发明申请

US20100009131A1 MULTI-EXPOSURE LITHOGRAPHY EMPLOYING A SINGLE ANTI-REFLECTIVE COATING LAYER 失效
标题翻译：采用单反反射涂层的多次曝光光刻
公开(公告)号：US20100009131A1
公开(公告)日：2010-01-14
申请号：US12169888
申请日：2008-07-09
申请人： Veeraraghavan S. Basker , Willard E. Conley , Steven J. Holmes , David V. Horak
发明人： Veeraraghavan S. Basker , Willard E. Conley , Steven J. Holmes , David V. Horak
IPC分类号： G03F7/20 , B32B9/00
CPC分类号： G03F7/20 , G03F7/70466 , G03F7/70958 , H01L21/76816 , H01L21/76838 , Y10T428/24802
摘要： A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer.
摘要翻译：将第一光致抗蚀剂施加在光致密层上并且被光刻图案化以形成具有接近两倍最小特征尺寸的间距的第一光致抗蚀剂部分的阵列。第一光致抗蚀剂部分或第一图案中的图案被转移到ARC层中并部分地转移到光致密层中。施加第二光致抗蚀剂并将其图案化成具有接近最小特征尺寸的两倍的间距的另一阵列并与第一图案隔行扫描。第二光致抗蚀剂或第二图案中的图案通过ARC部分转移并部分地转移到光致密层中。 ARC部分用包括第一图案和第二图案的复合图案图案化。复合图案通过光致密层转移到底层中以在底层中形成亚光刻图案。

8. 发明授权

US08507187B2 Multi-exposure lithography employing a single anti-reflective coating layer 失效
标题翻译：使用单个抗反射涂层的多曝光光刻
公开(公告)号：US08507187B2
公开(公告)日：2013-08-13
申请号：US12169888
申请日：2008-07-09
申请人： Veeraraghavan S. Basker , Willard E. Conley , Steven J. Holmes , David V. Horak
发明人： Veeraraghavan S. Basker , Willard E. Conley , Steven J. Holmes , David V. Horak
IPC分类号： G03F7/20
CPC分类号： G03F7/20 , G03F7/70466 , G03F7/70958 , H01L21/76816 , H01L21/76838 , Y10T428/24802
摘要： A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer.
摘要翻译：将第一光致抗蚀剂施加在光致密层上并且被光刻图案化以形成具有接近两倍最小特征尺寸的间距的第一光致抗蚀剂部分的阵列。第一光致抗蚀剂部分或第一图案中的图案被转移到ARC层中并部分地转移到光致密层中。施加第二光致抗蚀剂并将其图案化成具有接近最小特征尺寸的两倍的间距的另一阵列并与第一图案隔行扫描。第二光致抗蚀剂或第二图案中的图案通过ARC部分转移并部分地转移到光致密层中。 ARC部分用包括第一图案和第二图案的复合图案图案化。复合图案通过光致密层转移到底层中以在底层中形成亚光刻图案。

9. 发明授权

US08900961B2 Selective deposition of germanium spacers on nitride 有权
标题翻译：锗间隔物选择性沉积在氮化物上
公开(公告)号：US08900961B2
公开(公告)日：2014-12-02
申请号：US12907186
申请日：2010-10-19
申请人： Ashima B. Chakravarti , Anthony I. Chou , Toshiharu Furukawa , Steven J. Holmes , Wesley C. Natzle
发明人： Ashima B. Chakravarti , Anthony I. Chou , Toshiharu Furukawa , Steven J. Holmes , Wesley C. Natzle
IPC分类号： H01L21/336 , H01L29/66 , H01L21/02 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/02532 , H01L21/02587 , H01L21/0262 , H01L21/02639 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L2224/05571 , H01L2224/05573 , H01L2224/10126 , H01L2224/13023 , H01L2924/1305 , H01L2924/00
摘要： A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.
摘要翻译：在半导体制造工艺中选择性地形成锗结构的方法在化学氧化物去除（COR）工艺中从氮化物表面去除天然氧化物，然后将加热的氮化物和氧化物表面暴露于加热的含锗气体，以仅选择性地形成锗氮化物表面而不是氧化物表面。

10. 发明授权

US08541823B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08541823B2
公开(公告)日：2013-09-24
申请号：US13179635
申请日：2011-07-11
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
摘要翻译：晶体管。晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

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