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1. 发明授权

US08438419B2 Fault management for a communication bus 有权
标题翻译：通讯总线故障管理
公开(公告)号：US08438419B2
公开(公告)日：2013-05-07
申请号：US12997993
申请日：2008-06-30
申请人： Valerie Bernon-Enjalbert , Thierry Cassagnes , Philippe Lance
发明人： Valerie Bernon-Enjalbert , Thierry Cassagnes , Philippe Lance
IPC分类号： H04L29/14
CPC分类号： H04L12/403 , H01L2224/48137 , H01L2224/49175 , H01L2924/13091 , H04L12/10 , H04L25/0272 , H04L25/028 , H04L25/08 , H01L2924/00
摘要： A differential communication bus comprising a master module and a plurality of slave modules connected to at least first and second conductors whereby to communicate between the master and slave modules. The master module comprises a driver for applying first and second voltages respectively to the first and second conductors and for sourcing and sinking currents in the first and second conductors. The driver controls a difference between the first and second voltages and a common mode value of the first and second voltages. The driver includes first sourcing and sinking current limiters and second sourcing and sinking current limiters for limiting the currents in the first and second conductors. The master module is selectively responsive to a fault condition triggering simultaneous activation of the first and second sourcing current limiters or of the first and second sinking current limiters to disable the driver.
摘要翻译：差分通信总线包括主模块和连接到至少第一和第二导体的多个从模块，从而在主模块和从模块之间进行通信。主模块包括用于将第一和第二电压分别施加到第一和第二导体并用于在第一和第二导体中的电流和吸收电流的驱动器。驱动器控制第一和第二电压之间的差异以及第一和第二电压的共模值。该驱动器包括用于限制第一和第二导体中的电流的第一采样和吸收限流器以及第二采集和吸收限流器。主模块选择性地响应于触发同时激活第一和第二源电流限制器或第一和第二吸收电流限制器的故障条件以禁用驱动器。

2. 发明申请

US20110138090A1 COMMUNICATING ON AN ELECTRICAL BUS 有权
标题翻译：电气总线通讯
公开(公告)号：US20110138090A1
公开(公告)日：2011-06-09
申请号：US13059084
申请日：2008-08-22
申请人： Philippe Lance , Valerie Bernon-Enjalbert , Thierry Cassagnes
发明人： Philippe Lance , Valerie Bernon-Enjalbert , Thierry Cassagnes
IPC分类号： G06F13/00
CPC分类号： G06F13/364 , H04L12/403 , H04L25/4902 , H04L2012/40273
摘要： Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time.
摘要翻译：用于通过在脉冲宽度调制信号形式的电母线上产生主逻辑信号在电母线上进行通信的方法和装置。以电流信号的形式在电气总线上产生从属逻辑信号。通过对电气总线上的电流信号的大小进行采样来读取从属逻辑信号，其中当总线上的电压保持恒定一段时间时，电气总线上的电流大小在位时间的某一点被采样比在比特时间期间电压保持在任何电平的最短时间。

3. 发明申请

US20110121858A1 BUFFER APPARATUS, INTEGRATED CIRCUIT AND METHOD OF REDUCING A PORTION OF AN OSCILLATION OF AN OUTPUT SIGNAL 有权
标题翻译：缓冲器装置，集成电路和减少输出信号振荡部分的方法
公开(公告)号：US20110121858A1
公开(公告)日：2011-05-26
申请号：US13056334
申请日：2008-07-31
申请人： Thierry Cassagnes , Valerie Bernon-Enjalbert , Philippe Lance , Matthijs Pardoen
发明人： Thierry Cassagnes , Valerie Bernon-Enjalbert , Philippe Lance , Matthijs Pardoen
IPC分类号： H03K19/0175
CPC分类号： H03K19/00361 , H03K17/167 , H03K2217/94094
摘要： A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.
摘要翻译：用于通信总线的缓冲装置包括具有输出的驱动器电路。具有输入的放大器电路耦合到驱动器电路的输出端。驱动器电路被布置成在使用时产生具有包括其中的步骤的波形的驱动信号，以便基本上抑制放大器电路产生输出信号的振荡的一部分。

4. 发明申请

US20110093739A1 FAULT MANAGEMENT FOR A COMMUNICATION BUS 有权
标题翻译：通信总线故障管理
公开(公告)号：US20110093739A1
公开(公告)日：2011-04-21
申请号：US12997993
申请日：2008-06-30
申请人： Valerie Bernon-Enjalbert , Thierry Cassagnes , Philippe Lance
发明人： Valerie Bernon-Enjalbert , Thierry Cassagnes , Philippe Lance
IPC分类号： G06F11/16 , G06F13/00 , G06F11/00
CPC分类号： H04L12/403 , H01L2224/48137 , H01L2224/49175 , H01L2924/13091 , H04L12/10 , H04L25/0272 , H04L25/028 , H04L25/08 , H01L2924/00
摘要： A differential communication bus comprising a master module and a plurality of slave modules connected to at least first and second conductors whereby to communicate between the master and slave modules. The master module comprises a driver for applying first and second voltages respectively to the first and second conductors and for sourcing and sinking currents in the first and second conductors. The driver controls a difference between the first and second voltages and a common mode value of the first and second voltages. The driver includes first sourcing and sinking current limiters and second sourcing and sinking current limiters for limiting the currents in the first and second conductors. The master module is selectively responsive to a fault condition triggering simultaneous activation of the first and second sourcing current limiters or of the first and second sinking current limiters to disable the driver.
摘要翻译：差分通信总线包括主模块和连接到至少第一和第二导体的多个从模块，从而在主模块和从模块之间进行通信。主模块包括用于将第一和第二电压分别施加到第一和第二导体并用于在第一和第二导体中的电流和吸收电流的驱动器。驱动器控制第一和第二电压之间的差异以及第一和第二电压的共模值。该驱动器包括用于限制第一和第二导体中的电流的第一采样和吸收限流器以及第二采集和吸收限流器。主模块选择性地响应于触发同时激活第一和第二源电流限制器或第一和第二吸收电流限制器的故障条件以禁用驱动器。

5. 发明授权

US08612657B2 System and method for communicating on an electrical bus 有权
标题翻译：用于在电气总线上通信的系统和方法
公开(公告)号：US08612657B2
公开(公告)日：2013-12-17
申请号：US13059084
申请日：2008-08-22
申请人： Philippe Lance , Valerie Bernon-Enjalbert , Thierry Cassagnes
发明人： Philippe Lance , Valerie Bernon-Enjalbert , Thierry Cassagnes
IPC分类号： G06F13/00 , G06F13/364
CPC分类号： G06F13/364 , H04L12/403 , H04L25/4902 , H04L2012/40273
摘要： Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time.
摘要翻译：用于通过在脉冲宽度调制信号形式的电母线上产生主逻辑信号在电母线上进行通信的方法和装置。以电流信号的形式在电气总线上产生从属逻辑信号。通过对电气总线上的电流信号的大小进行采样来读取从属逻辑信号，其中当总线上的电压保持恒定一段时间时，电气总线上的电流大小在位时间的某一点被采样比在比特时间期间电压保持在任何电平的最短时间。

6. 发明授权

US08193828B2 Buffer apparatus, integrated circuit and method of reducing a portion of an oscillation of an output signal 有权
标题翻译：缓冲装置，集成电路和减少输出信号振荡的一部分的方法
公开(公告)号：US08193828B2
公开(公告)日：2012-06-05
申请号：US13056334
申请日：2008-07-31
申请人： Thierry Cassagnes , Valerie Bernon-Enjalbert , Philippe Lance , Matthijs Pardoen
发明人： Thierry Cassagnes , Valerie Bernon-Enjalbert , Philippe Lance , Matthijs Pardoen
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00361 , H03K17/167 , H03K2217/94094
摘要： A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.
摘要翻译：用于通信总线的缓冲装置包括具有输出的驱动器电路。具有输入的放大器电路耦合到驱动器电路的输出端。驱动器电路被布置成在使用时产生具有包括其中的步骤的波形的驱动信号，以便基本上抑制放大器电路产生输出信号的振荡的一部分。

7. 发明授权

US09318448B2 Packaged semiconductor device, a semiconductor device and a method of manufacturing a packaged semiconductor device 有权
标题翻译：封装半导体器件，半导体器件和制造封装半导体器件的方法
公开(公告)号：US09318448B2
公开(公告)日：2016-04-19
申请号：US14401132
申请日：2012-05-30
申请人： Patrice Besse , Kamel Abouda , Valerie Bernon-Enjalbert , Philippe Givelin
发明人： Patrice Besse , Kamel Abouda , Valerie Bernon-Enjalbert , Philippe Givelin
IPC分类号： H01L23/60 , H01L27/02 , H01L21/761 , H01L21/762 , H01L27/04 , H01L29/74
CPC分类号： H01L23/60 , H01L21/761 , H01L21/76229 , H01L27/0262 , H01L27/04 , H01L29/74 , H01L29/7436 , H01L2224/48091 , H01L2224/49113 , H01L2924/13034 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region. At least part of the second P-type region is arranged in between the first semiconductor component and the second semiconductor component, and at least part of the third N-type region is arranged in between the at least part of the first P-type region and the second semiconductor component.
摘要翻译：描述了包括封装和半导体器件的封装半导体器件。半导体器件包括分别与第一和第二接合线接合到一个或多个GND引脚的第一和第二GND焊盘，用第三接合线接合到第一功能引脚的第一功能焊盘，半导体层 P型导电性，第一半导体元件和第二半导体元件。第一半导体部件被布置成当瞬态电流被施加到第一功能引脚时，至少一部分瞬态电流从第一P区转移到第一GND焊盘，至少一个第一PN结。第二半导体部件包括与第一功能焊盘相关联的第二半导体部件的端子的第二N型区域。第一GND焊盘与第二P型区域接触。第二GND焊盘与第三N型区域接触。第二P型区域的至少一部分配置在第一半导体部件和第二半导体部件之间，第三N型区域的至少一部分配置在第一P型区域的至少一部分之间和第二半导体部件。

8. 发明申请

US20150002116A1 DC TO DC CONVERTER AND METHOD TO OPERATE A DC TO DC CONVERTER 有权
标题翻译： DC-DC转换器和操作DC-DC转换器的方法
公开(公告)号：US20150002116A1
公开(公告)日：2015-01-01
申请号：US14372765
申请日：2012-01-20
申请人： Valerie Bernon-Enjalbert , Franck Galtie , Philippe Goyhenetche
发明人： Valerie Bernon-Enjalbert , Franck Galtie , Philippe Goyhenetche
IPC分类号： H02M3/158
CPC分类号： H02M3/1582 , H02M2001/0022
摘要： A DC to DC converter including a buck converter, a boost converter, and a control unit, wherein the control unit is arranged to calculate an error voltage of the buck converter Verr_buck based on a feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the buck converter Vref_buck, and wherein the control unit is arranged to calculate an error voltage of the boost converter Verr_boost based on the feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the boost converter Vref_boost, wherein the reference voltage of the boost converter Vref_boost is shifted by an offset Voffset as compared to the reference voltage of the buck converter Vref_buck.
摘要翻译：一种包括降压转换器，升压转换器和控制单元的DC-DC转换器，其中所述控制单元被布置为基于所述DC-DC转换器的反馈输出电压Vout_FB来计算所述降压转换器Verr_buck的误差电压，以及降压转换器Vref_buck的参考电压，并且其中控制单元布置成基于DC-DC转换器的反馈输出电压Vout_FB和升压转换器Vref_boost的参考电压来计算升压转换器Verr_boost的误差电压，其中，与降压转换器Vref_buck的参考电压相比，升压转换器Vref_boost的参考电压偏移了偏移Voffset。

9. 发明申请

US20140300193A1 POWER SAFETY CIRCUIT, INTEGRATED CIRCUIT DEVICE AND SAFETY CRITICAL SYSTEM 有权
标题翻译：电力安全电路，集成电路设备和安全关键系统
公开(公告)号：US20140300193A1
公开(公告)日：2014-10-09
申请号：US14354278
申请日：2011-10-27
申请人： Philippe Givelin , Valerie Bernon-Enjalbert , Guillaume Founaud
发明人： Philippe Givelin , Valerie Bernon-Enjalbert , Guillaume Founaud
IPC分类号： H02J9/06
CPC分类号： H02J9/061 , B60R21/0173 , B60T8/885 , B60T2270/414 , Y10T307/615
摘要： A power safety circuit comprises a power sense terminal; an output terminal; an output driver unit connected to the output terminal; an input terminal connectable to receive a first power from a power source and arranged to supply the first power to the output driver unit; and a power detection unit arranged to detect a state of the input terminal and provide a power sense signal to the power sense terminal; wherein the power sense terminal is arranged to supply a second power to the output driver unit when the power sense signal indicates a level of the first power below a minimum level for driving the output terminal. An integrated circuit device comprises at least one power safety circuit. A safety critical system comprises at least one integrated circuit device with at least one power safety circuit.
摘要翻译：电源安全电路包括电源检测端子; 输出端子; 连接到输出端子的输出驱动器单元; 输入端子，其可连接以从电源接收第一功率并被布置成将第一功率提供给所述输出驱动器单元; 以及功率检测单元，被配置为检测所述输入端子的状态并向所述功率检测端子提供功率检测信号; 其中所述功率检测端子被布置成当所述功率检测信号指示所述第一功率的电平低于用于驱动所述输出端子的最小电平时，向所述输出驱动器单元提供第二功率。集成电路装置包括至少一个电力安全电路。安全关键系统包括具有至少一个电力安全电路的至少一个集成电路装置。

10. 发明授权

US09425692B2 DC to DC converter and method to transition the DC to DC converter from a buck mode to a boost mode 有权
标题翻译：直流到直流转换器以及从降压模式转换到升压模式的DC到DC转换器的方法
公开(公告)号：US09425692B2
公开(公告)日：2016-08-23
申请号：US14372765
申请日：2012-01-20
申请人： Valerie Bernon-Enjalbert , Franck Galtie , Philippe Goyhenetche
发明人： Valerie Bernon-Enjalbert , Franck Galtie , Philippe Goyhenetche
IPC分类号： H02M3/158 , H02M1/00
CPC分类号： H02M3/1582 , H02M2001/0022
摘要： A DC to DC converter including a buck converter, a boost converter, and a control unit, wherein the control unit is arranged to calculate an error voltage of the buck converter Verr_buck based on a feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the buck converter Vref_buck, and wherein the control unit is arranged to calculate an error voltage of the boost converter Verr_boost based on the feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the boost converter Vref_boost, wherein the reference voltage of the boost converter Vref_boost is shifted by an offset Voffset as compared to the reference voltage of the buck converter Vref_buck.
摘要翻译：一种包括降压转换器，升压转换器和控制单元的DC-DC转换器，其中所述控制单元被布置为基于所述DC-DC转换器的反馈输出电压Vout_FB来计算所述降压转换器Verr_buck的误差电压，以及降压转换器Vref_buck的参考电压，并且其中控制单元布置成基于DC-DC转换器的反馈输出电压Vout_FB和升压转换器Vref_boost的参考电压来计算升压转换器Verr_boost的误差电压，其中，与降压转换器Vref_buck的参考电压相比，升压转换器Vref_boost的参考电压偏移了偏移Voffset。

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