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1. 发明授权

US08438419B2 Fault management for a communication bus 有权
标题翻译：通讯总线故障管理
公开(公告)号：US08438419B2
公开(公告)日：2013-05-07
申请号：US12997993
申请日：2008-06-30
申请人： Valerie Bernon-Enjalbert , Thierry Cassagnes , Philippe Lance
发明人： Valerie Bernon-Enjalbert , Thierry Cassagnes , Philippe Lance
IPC分类号： H04L29/14
CPC分类号： H04L12/403 , H01L2224/48137 , H01L2224/49175 , H01L2924/13091 , H04L12/10 , H04L25/0272 , H04L25/028 , H04L25/08 , H01L2924/00
摘要： A differential communication bus comprising a master module and a plurality of slave modules connected to at least first and second conductors whereby to communicate between the master and slave modules. The master module comprises a driver for applying first and second voltages respectively to the first and second conductors and for sourcing and sinking currents in the first and second conductors. The driver controls a difference between the first and second voltages and a common mode value of the first and second voltages. The driver includes first sourcing and sinking current limiters and second sourcing and sinking current limiters for limiting the currents in the first and second conductors. The master module is selectively responsive to a fault condition triggering simultaneous activation of the first and second sourcing current limiters or of the first and second sinking current limiters to disable the driver.
摘要翻译：差分通信总线包括主模块和连接到至少第一和第二导体的多个从模块，从而在主模块和从模块之间进行通信。主模块包括用于将第一和第二电压分别施加到第一和第二导体并用于在第一和第二导体中的电流和吸收电流的驱动器。驱动器控制第一和第二电压之间的差异以及第一和第二电压的共模值。该驱动器包括用于限制第一和第二导体中的电流的第一采样和吸收限流器以及第二采集和吸收限流器。主模块选择性地响应于触发同时激活第一和第二源电流限制器或第一和第二吸收电流限制器的故障条件以禁用驱动器。

2. 发明申请

US20110138090A1 COMMUNICATING ON AN ELECTRICAL BUS 有权
标题翻译：电气总线通讯
公开(公告)号：US20110138090A1
公开(公告)日：2011-06-09
申请号：US13059084
申请日：2008-08-22
申请人： Philippe Lance , Valerie Bernon-Enjalbert , Thierry Cassagnes
发明人： Philippe Lance , Valerie Bernon-Enjalbert , Thierry Cassagnes
IPC分类号： G06F13/00
CPC分类号： G06F13/364 , H04L12/403 , H04L25/4902 , H04L2012/40273
摘要： Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time.
摘要翻译：用于通过在脉冲宽度调制信号形式的电母线上产生主逻辑信号在电母线上进行通信的方法和装置。以电流信号的形式在电气总线上产生从属逻辑信号。通过对电气总线上的电流信号的大小进行采样来读取从属逻辑信号，其中当总线上的电压保持恒定一段时间时，电气总线上的电流大小在位时间的某一点被采样比在比特时间期间电压保持在任何电平的最短时间。

3. 发明申请

US20110121858A1 BUFFER APPARATUS, INTEGRATED CIRCUIT AND METHOD OF REDUCING A PORTION OF AN OSCILLATION OF AN OUTPUT SIGNAL 有权
标题翻译：缓冲器装置，集成电路和减少输出信号振荡部分的方法
公开(公告)号：US20110121858A1
公开(公告)日：2011-05-26
申请号：US13056334
申请日：2008-07-31
申请人： Thierry Cassagnes , Valerie Bernon-Enjalbert , Philippe Lance , Matthijs Pardoen
发明人： Thierry Cassagnes , Valerie Bernon-Enjalbert , Philippe Lance , Matthijs Pardoen
IPC分类号： H03K19/0175
CPC分类号： H03K19/00361 , H03K17/167 , H03K2217/94094
摘要： A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.
摘要翻译：用于通信总线的缓冲装置包括具有输出的驱动器电路。具有输入的放大器电路耦合到驱动器电路的输出端。驱动器电路被布置成在使用时产生具有包括其中的步骤的波形的驱动信号，以便基本上抑制放大器电路产生输出信号的振荡的一部分。

4. 发明申请

US20110093739A1 FAULT MANAGEMENT FOR A COMMUNICATION BUS 有权
标题翻译：通信总线故障管理
公开(公告)号：US20110093739A1
公开(公告)日：2011-04-21
申请号：US12997993
申请日：2008-06-30
申请人： Valerie Bernon-Enjalbert , Thierry Cassagnes , Philippe Lance
发明人： Valerie Bernon-Enjalbert , Thierry Cassagnes , Philippe Lance
IPC分类号： G06F11/16 , G06F13/00 , G06F11/00
CPC分类号： H04L12/403 , H01L2224/48137 , H01L2224/49175 , H01L2924/13091 , H04L12/10 , H04L25/0272 , H04L25/028 , H04L25/08 , H01L2924/00
摘要： A differential communication bus comprising a master module and a plurality of slave modules connected to at least first and second conductors whereby to communicate between the master and slave modules. The master module comprises a driver for applying first and second voltages respectively to the first and second conductors and for sourcing and sinking currents in the first and second conductors. The driver controls a difference between the first and second voltages and a common mode value of the first and second voltages. The driver includes first sourcing and sinking current limiters and second sourcing and sinking current limiters for limiting the currents in the first and second conductors. The master module is selectively responsive to a fault condition triggering simultaneous activation of the first and second sourcing current limiters or of the first and second sinking current limiters to disable the driver.
摘要翻译：差分通信总线包括主模块和连接到至少第一和第二导体的多个从模块，从而在主模块和从模块之间进行通信。主模块包括用于将第一和第二电压分别施加到第一和第二导体并用于在第一和第二导体中的电流和吸收电流的驱动器。驱动器控制第一和第二电压之间的差异以及第一和第二电压的共模值。该驱动器包括用于限制第一和第二导体中的电流的第一采样和吸收限流器以及第二采集和吸收限流器。主模块选择性地响应于触发同时激活第一和第二源电流限制器或第一和第二吸收电流限制器的故障条件以禁用驱动器。

5. 发明授权

US08612657B2 System and method for communicating on an electrical bus 有权
标题翻译：用于在电气总线上通信的系统和方法
公开(公告)号：US08612657B2
公开(公告)日：2013-12-17
申请号：US13059084
申请日：2008-08-22
申请人： Philippe Lance , Valerie Bernon-Enjalbert , Thierry Cassagnes
发明人： Philippe Lance , Valerie Bernon-Enjalbert , Thierry Cassagnes
IPC分类号： G06F13/00 , G06F13/364
CPC分类号： G06F13/364 , H04L12/403 , H04L25/4902 , H04L2012/40273
摘要： Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time.
摘要翻译：用于通过在脉冲宽度调制信号形式的电母线上产生主逻辑信号在电母线上进行通信的方法和装置。以电流信号的形式在电气总线上产生从属逻辑信号。通过对电气总线上的电流信号的大小进行采样来读取从属逻辑信号，其中当总线上的电压保持恒定一段时间时，电气总线上的电流大小在位时间的某一点被采样比在比特时间期间电压保持在任何电平的最短时间。

6. 发明授权

US08193828B2 Buffer apparatus, integrated circuit and method of reducing a portion of an oscillation of an output signal 有权
标题翻译：缓冲装置，集成电路和减少输出信号振荡的一部分的方法
公开(公告)号：US08193828B2
公开(公告)日：2012-06-05
申请号：US13056334
申请日：2008-07-31
申请人： Thierry Cassagnes , Valerie Bernon-Enjalbert , Philippe Lance , Matthijs Pardoen
发明人： Thierry Cassagnes , Valerie Bernon-Enjalbert , Philippe Lance , Matthijs Pardoen
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00361 , H03K17/167 , H03K2217/94094
摘要： A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.
摘要翻译：用于通信总线的缓冲装置包括具有输出的驱动器电路。具有输入的放大器电路耦合到驱动器电路的输出端。驱动器电路被布置成在使用时产生具有包括其中的步骤的波形的驱动信号，以便基本上抑制放大器电路产生输出信号的振荡的一部分。

7. 发明授权

US06750664B2 Apparatus for managing an intergrated circuit 有权
标题翻译：用于管理集成电路的装置
公开(公告)号：US06750664B2
公开(公告)日：2004-06-15
申请号：US09934159
申请日：2001-08-21
申请人： Philippe Lance , Philippe Meunier
发明人： Philippe Lance , Philippe Meunier
IPC分类号： G01R2708
CPC分类号： G01N25/72
摘要： An apparatus for an integrated circuit comprising a thermal sensor (41-44), an A-D converter (58) coupled to the thermal sensor, wherein the thermal sensor provides an input to the A-D converter, and the A-D converter converts the input to a digital value representative of the thermal environment of the thermal sensor. The integrated circuit collects a data value at a location on an integrated circuit wherein the data value has a predetermined functional relationship to the temperature at the location. The integrated circuit converts the data value to a value representative of the thermal environment of the location on the integrated circuit.
摘要翻译：一种用于集成电路的装置，包括热传感器（41-44），耦合到所述热传感器的AD转换器（58），其中所述热传感器向所述AD转换器提供输入，并且所述AD转换器将所述输入转换为数字代表热传感器的热环境的值。集成电路在集成电路的位置处收集数据值，其中数据值与该位置处的温度具有预定的功能关系。集成电路将数据值转换为代表集成电路上位置的热环境的值。

8. 发明授权

US09157955B2 Chip damage detection device for a semiconductor integrated circuit 有权
标题翻译：一种用于半导体集成电路的芯片损坏检测装置
公开(公告)号：US09157955B2
公开(公告)日：2015-10-13
申请号：US13522865
申请日：2010-01-21
申请人： Erwan Hemon , Philippe Lance , Kurt Neugebauer
发明人： Erwan Hemon , Philippe Lance , Kurt Neugebauer
IPC分类号： G01R31/20 , G01R31/28 , G01R31/317
CPC分类号： G01R31/31717 , H01L2924/0002 , H01L2924/00
摘要： A chip damage detection device is provided that includes at least one bi-stable circuit having a first conductive line passing through an observed area of a semiconductor integrated circuit chip for damage monitoring of the observed area. The at least one bi-stable circuit is arranged to flip from a first stable state into a second stable state when a potential difference between a first end and a second end of the first conductive line changes or when a leakage current overdrives a state keeping current at the first conductive line. Further, a semiconductor integrated circuit device that includes the chip damage detection device and a safety critical system that includes the semiconductor integrated circuit device or the chip damage detection circuit is provided.
摘要翻译：提供一种芯片损伤检测装置，其包括至少一个双稳电路，该双稳态电路具有穿过半导体集成电路芯片的观察区域的第一导线，用于对观察区域进行损伤监测。当第一导电线的第一端和第二端之间的电位差发生变化时，或当泄漏电流过驱动保持电流时，至少一个双稳态电路被布置成从第一稳定状态翻转到第二稳定状态在第一导线上。此外，提供了包括芯片损坏检测装置和包括半导体集成电路装置或芯片损坏检测电路的安全关键系统的半导体集成电路装置。

9. 发明申请

US20100128402A1 INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND ESD PROTECTION THEREFOR 有权
标题翻译：集成电路，电子设备及其ESD保护
公开(公告)号：US20100128402A1
公开(公告)日：2010-05-27
申请号：US12597006
申请日：2007-04-27
申请人： Patrice Besse , Erwan Hemon , Philippe Lance
发明人： Patrice Besse , Erwan Hemon , Philippe Lance
IPC分类号： H02H9/00
CPC分类号： H01L27/0251
摘要： An integrated circuit comprises electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to one or more external connector(s) of the integrated circuit. The ESD protection circuitry comprises at least one ESD protection component coupled to the one or more external connectors for providing ESD protection thereto. The ESD protection circuitry further comprises an ESD connector, coupled to the one or more external connector(s), arranged to couple supplementary ESD protection to the one or more external connector(s).
摘要翻译：集成电路包括静电放电（ESD）保护电路，其布置成向集成电路的一个或多个外部连接器提供ESD保护。 ESD保护电路包括耦合到一个或多个外部连接器的至少一个ESD保护部件，用于向其提供ESD保护。 ESD保护电路还包括耦合到所述一个或多个外部连接器的ESD连接器，其布置成将辅助ESD保护耦合到所述一个或多个外部连接器。

10. 发明授权

US08307227B2 Data communication system and method 有权
标题翻译：数据通信系统及方法
公开(公告)号：US08307227B2
公开(公告)日：2012-11-06
申请号：US12514039
申请日：2006-11-08
申请人： Philippe Lance , Arlette Marty-Blavier
发明人： Philippe Lance , Arlette Marty-Blavier
IPC分类号： G06F1/26 , H04L25/34
CPC分类号： H04L7/06
摘要： A data communication system includes one or more data processing units and includes a central control unit. The decentralized data processing units are connected to the central control unit by data connection. The central control unit includes a synchronisation unit for outputting via the data connection an synchronisation signal to the data processing unit. The data processing unit includes a data generator for generating data and transmitting, after the synchronisation signal, data to the central control unit.
摘要翻译：数据通信系统包括一个或多个数据处理单元，并且包括中央控制单元。分散数据处理单元通过数据连接连接到中央控制单元。中央控制单元包括同步单元，用于经由数据连接将同步信号输出到数据处理单元。数据处理单元包括用于产生数据并在同步信号之后将数据发送到中央控制单元的数据发生器。

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