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1. 发明授权

US06605396B2 Resolution enhancement for alternating phase shift masks 有权
标题翻译：交替相移掩模的分辨率增强
公开(公告)号：US06605396B2
公开(公告)日：2003-08-12
申请号：US09923527
申请日：2001-08-06
申请人： Uwe Paul Schroeder , Tobias Mono , Veit Klee
发明人： Uwe Paul Schroeder , Tobias Mono , Veit Klee
IPC分类号： G03F900
CPC分类号： G03F1/34 , G03F1/32
摘要： An alternating phase shift mask (400) and method of manufacturing thereof including assist edges (450) and (452) surrounding a main phase edge (420). Assist edges (450) and (452) improve the resolution of the alternating phase shift mask (400), thus enabling the patterning of smaller size features on a semiconductor wafer.
摘要翻译：一种交替相移掩模（400）及其制造方法，包括围绕主相边缘（420）的辅助边缘（450）和（452）。辅助边缘（450）和（452）提高交替相移掩模（400）的分辨率，因此能够对半导体晶片上的较小尺寸特征图案化。

2. 发明授权

US07678704B2 Method of making a contact in a semiconductor device 有权
标题翻译：在半导体器件中进行接触的方法
公开(公告)号：US07678704B2
公开(公告)日：2010-03-16
申请号：US11301515
申请日：2005-12-13
申请人： Veit Klee , Roman Knoefler , Uwe Paul Schroeder
发明人： Veit Klee , Roman Knoefler , Uwe Paul Schroeder
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/76816 , H01L21/76895 , H01L21/76897
摘要： To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.
摘要翻译：为了形成半导体器件，在导电区域上形成绝缘层，并且在绝缘层上形成图案转移层。图案转印层以要形成在绝缘层中的凹槽布局的相反色调被图案化，使得图案转印层保留在要形成凹部的区域上。掩模材料形成在绝缘层上并与图案转印层对准。去除图案转印层的剩余部分，并使用掩模材料作为掩模在绝缘层中蚀刻凹陷。

3. 发明授权

US07985676B2 Method of making a contact in a semiconductor device 有权
标题翻译：在半导体器件中进行接触的方法
公开(公告)号：US07985676B2
公开(公告)日：2011-07-26
申请号：US12693231
申请日：2010-01-25
申请人： Veit Klee , Roman Knoefler , Uwe Paul Schroeder
发明人： Veit Klee , Roman Knoefler , Uwe Paul Schroeder
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/76816 , H01L21/76895 , H01L21/76897
摘要： To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.
摘要翻译：为了形成半导体器件，在导电区域上形成绝缘层，并且在绝缘层上形成图案转移层。图案转印层以要形成在绝缘层中的凹槽布局的相反色调被图案化，使得图案转印层保留在要形成凹部的区域上。掩模材料形成在绝缘层上并与图案转印层对准。去除图案转印层的剩余部分，并使用掩模材料作为掩模在绝缘层中蚀刻凹陷。

4. 发明授权

US06566227B2 Strap resistance using selective oxidation to cap DT poly before STI etch 有权
标题翻译：在STI蚀刻之前，使用选择性氧化覆盖DT poly的带状电阻
公开(公告)号：US06566227B2
公开(公告)日：2003-05-20
申请号：US09929334
申请日：2001-08-13
申请人： Paul Wensley , Martin Commons , Tobias Mono , Veit Klee
发明人： Paul Wensley , Martin Commons , Tobias Mono , Veit Klee
IPC分类号： H01L2176
CPC分类号： H01L27/10864 , H01L21/76224 , H01L21/763 , H01L27/10861
摘要： A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (114) in a region between the trenches (113). A second semiconductor material (116) is deposited over the trenches (113) to fill the trenches (113) to a height below the first semiconductor material (112) top surface. A first insulator (130) is selectively formed over the second semiconductor material (116). The pad nitride (114) and a portion of the first semiconductor material (112) between the trenches (113) are removed to isolate element regions of the wafer (100) and form straps (142) having a low resistance.
摘要翻译：一种为半导体晶片（100）提供浅沟槽（143）隔离的方法。沟槽（113）形成在第一半导体材料（112）和衬垫氮化物（114）内，在沟槽（113）之间的区域中留下第一半导体材料（112）的一部分和衬垫氮化物（114）。第二半导体材料（116）沉积在沟槽（113）上以将沟槽（113）填充到低于第一半导体材料（112）顶表面的高度。在第二半导体材料（116）上有选择地形成第一绝缘体（130）。去除衬垫氮化物（114）和沟槽（113）之间的第一半导体材料（112）的一部分以隔离晶片（100）的元件区域并形成具有低电阻的带（142）。

5. 发明申请

US20100124820A1 Method of Making a Contact in a Semiconductor Device 有权
标题翻译：在半导体器件中进行接触的方法
公开(公告)号：US20100124820A1
公开(公告)日：2010-05-20
申请号：US12693231
申请日：2010-01-25
申请人： Veit Klee , Roman Knoefler , Uwe Paul Schroeder
发明人： Veit Klee , Roman Knoefler , Uwe Paul Schroeder
IPC分类号： H01L21/768
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/76816 , H01L21/76895 , H01L21/76897
摘要： To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.
摘要翻译：为了形成半导体器件，在导电区域上形成绝缘层，并且在绝缘层上形成图案转移层。图案转印层以要形成在绝缘层中的凹槽布局的相反色调被图案化，使得图案转印层保留在要形成凹部的区域上。掩模材料形成在绝缘层上并与图案转印层对准。去除图案转印层的剩余部分，并使用掩模材料作为掩模在绝缘层中蚀刻凹陷。

6. 发明授权

US06551874B2 Self-aligned STI process using nitride hard mask 失效
标题翻译：使用氮化物硬掩模的自对准STI工艺
公开(公告)号：US06551874B2
公开(公告)日：2003-04-22
申请号：US09888287
申请日：2001-06-22
申请人： John Pohl , Nirmal Chaudhary , Veit Klee , Tobias Mono , Paul Schroeder
发明人： John Pohl , Nirmal Chaudhary , Veit Klee , Tobias Mono , Paul Schroeder
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L21/76224
摘要： A nitride hard mask (230) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches (216) on a semiconductor wafer (200). The memory cell deep trenches (216) are separated from active areas (212) by a region of substrate (212). A nitride hard mask (230) is formed over the semiconductor wafer (200). The wafer (200) is patterned with the nitride hard mask (230), and the wafer (200) is etched to remove the region of substrate (212) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask (230) is used.
摘要翻译：氮化物硬掩模（230）用于隔离DRAM单元的有效区域。浅沟槽隔离（STI）方法包括在半导体晶片（200）上形成包括深沟槽（216）的存储单元。存储单元深沟槽（216）通过衬底（212）的区域与有源区域（212）分离。氮化物硬掩模（230）形成在半导体晶片（200）上。用氮化物硬掩模（230）对晶片（200）进行构图，并且蚀刻晶片（200）以去除深沟槽和有源区域之间的衬底（212）的区域，以提供浅沟槽隔离。使用对氮化物硬掩模（230）选择性的蚀刻化学品。

7. 发明授权

US07235472B2 Method of making fully silicided gate electrode 有权
标题翻译：制作完全硅化栅电极的方法
公开(公告)号：US07235472B2
公开(公告)日：2007-06-26
申请号：US10988113
申请日：2004-11-12
申请人： Veit Klee , Sun-Oo Kim
发明人： Veit Klee , Sun-Oo Kim
IPC分类号： H01L21/3205
CPC分类号： H01L29/6653 , H01L21/28097 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon layer formed on a gate dielectric layer over a substrate. Etching the second silicon layer is stopped at the etch stop oxide layer. A spacer structure is formed about the interim gate electrode stack, and then the top silicon portion and the sandwiched oxide portion are removed. The spacer structure height may be reduced. A metal layer is formed over the bottom silicon portion of the interim gate electrode stack and over source and drain regions of the substrate, all of which are silicided at the same time to form a fully silicided (FUSI) gate electrode and silicided source and drain regions.
摘要翻译：制造用于集成电路芯片的半导体器件的方法。形成的中间栅极电极堆叠包括从第二硅层图案化的顶部硅部分，从蚀刻停止氧化物层图案化的夹层氧化物部分和从在衬底上形成的栅极电介质层上形成的第一硅层图案化的底部硅部分。蚀刻第二硅层在蚀刻停止氧化物层处停止。围绕临时栅电极堆叠形成间隔结构，然后去除顶部硅部分和夹层氧化物部分。可以减小间隔件结构的高度。在中间栅极电极堆叠的底部硅部分上方和衬底的源极和漏极区域之上形成金属层，所有这些都被同时硅化以形成完全硅化（FUSI）栅极电极和硅化物源极和漏极地区。

8. 发明申请

US20070134909A1 Method of making a contact in a semiconductor device 有权
标题翻译：在半导体器件中进行接触的方法
公开(公告)号：US20070134909A1
公开(公告)日：2007-06-14
申请号：US11301515
申请日：2005-12-13
申请人： Veit Klee , Roman Knoefler , Uwe Schroeder
发明人： Veit Klee , Roman Knoefler , Uwe Schroeder
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/76816 , H01L21/76895 , H01L21/76897
摘要： To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.
摘要翻译：为了形成半导体器件，在导电区域上形成绝缘层，并且在绝缘层上形成图案转移层。图案转印层以要形成在绝缘层中的凹槽布局的相反色调被图案化，使得图案转印层保留在要形成凹部的区域上。掩模材料形成在绝缘层上并与图案转印层对准。去除图案转印层的剩余部分，并使用掩模材料作为掩模在绝缘层中蚀刻凹陷。

9. 发明申请

US20060105557A1 Method of making fully silicided gate electrode 有权
标题翻译：制作完全硅化栅电极的方法
公开(公告)号：US20060105557A1
公开(公告)日：2006-05-18
申请号：US10988113
申请日：2004-11-12
申请人： Veit Klee , Sun-Oo Kim
发明人： Veit Klee , Sun-Oo Kim
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/6653 , H01L21/28097 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon layer formed on a gate dielectric layer over a substrate. Etching the second silicon layer is stopped at the etch stop oxide layer. A spacer structure is formed about the interim gate electrode stack, and then the top silicon portion and the sandwiched oxide portion are removed. The spacer structure height may be reduced. A metal layer is formed over the bottom silicon portion of the interim gate electrode stack and over source and drain regions of the substrate, all of which are silicided at the same time to form a fully silicided (FUSI) gate electrode and silicided source and drain regions.
摘要翻译：制造用于集成电路芯片的半导体器件的方法。形成的中间栅极电极堆叠包括从第二硅层图案化的顶部硅部分，从蚀刻停止氧化物层图案化的夹层氧化物部分和从在衬底上形成的栅极电介质层上形成的第一硅层图案化的底部硅部分。蚀刻第二硅层在蚀刻停止氧化物层处停止。围绕临时栅电极堆叠形成间隔结构，然后去除顶部硅部分和夹层氧化物部分。可以减小间隔件结构的高度。在中间栅极电极堆叠的底部硅部分上方和衬底的源极和漏极区域之上形成金属层，所有这些都被同时硅化以形成完全硅化（FUSI）栅极电极和硅化物源极和漏极地区。

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