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1. 发明授权

US08598645B2 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US08598645B2
公开(公告)日：2013-12-03
申请号：US12910331
申请日：2010-10-22
申请人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

2. 发明授权

US07842618B2 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US07842618B2
公开(公告)日：2010-11-30
申请号：US11193409
申请日：2005-08-01
申请人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

3. 发明授权

US07679129B1 System and method for improving oxide-nitride-oxide (ONO) coupling in a semiconductor device 有权
标题翻译：用于改善半导体器件中的氧化物 - 氧化物 - 氧化物（ONO）耦合的系统和方法
公开(公告)号：US07679129B1
公开(公告)日：2010-03-16
申请号：US11128389
申请日：2005-05-13
申请人： Angela T. Hui , Unsoon Kim , Hiroyuki Kinoshita , Kuo-Tung Chang
发明人： Angela T. Hui , Unsoon Kim , Hiroyuki Kinoshita , Kuo-Tung Chang
IPC分类号： H01L29/94
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/66825
摘要： A memory device includes a substrate and a first dielectric layer formed over the substrate. At least two charge storage elements are formed over the first dielectric layer. The substrate and the first dielectric layer include a shallow trench filled with an oxide material. The oxide material formed in a center portion of the shallow trench is removed to provide a region with a substantially rectangular cross-section.
摘要翻译：存储器件包括衬底和形成在衬底上的第一电介质层。在第一电介质层上形成至少两个电荷存储元件。衬底和第一介电层包括填充有氧化物材料的浅沟槽。形成在浅沟槽的中心部分的氧化物材料被去除以提供具有基本上矩形横截面的区域。

4. 发明申请

US20070026675A1 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US20070026675A1
公开(公告)日：2007-02-01
申请号：US11193409
申请日：2005-08-01
申请人： Unsoon Kim , Angela Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L21/302
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

5. 发明授权

US08802537B1 System and method for improving reliability in a semiconductor device 有权
标题翻译：用于提高半导体器件的可靠性的系统和方法
公开(公告)号：US08802537B1
公开(公告)日：2014-08-12
申请号：US11189874
申请日：2005-07-27
申请人： Yider Wu , Unsoon Kim , Kuo-Tung Chang , Harpreet Sachar
发明人： Yider Wu , Unsoon Kim , Kuo-Tung Chang , Harpreet Sachar
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/02057
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。存储器件被预先清洁以准备用于其上形成氧化物的存储器件的表面，其中清洁存储器件去除沟槽相对侧上的阻挡氧化物层的部分。在沟槽的相对侧上修整氮化物层。在沟槽中形成衬里氧化物层。

6. 发明授权

US06664191B1 Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space 有权
标题翻译：非自对准浅沟槽隔离工艺与一次性空间定义亚光刻多孔空间
公开(公告)号：US06664191B1
公开(公告)日：2003-12-16
申请号：US09973131
申请日：2001-10-09
申请人： Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
发明人： Unsoon Kim , Yider Wu , Yu Sun , Michael K. Templeton , Angela T. Hui , Chi Chang
IPC分类号： H01L21302
CPC分类号： H01L27/11526 , H01L21/0337 , H01L21/0338 , H01L21/76229 , H01L21/76838 , H01L27/11531 , Y10S438/975
摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.
摘要翻译：提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。第一多晶硅层沉积在覆盖STI区域的衬底上。然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

7. 发明授权

US08759894B1 System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device 有权
标题翻译：用于减少半导体器件中的电荷存储元件之间的交叉耦合噪声的系统和方法
公开(公告)号：US08759894B1
公开(公告)日：2014-06-24
申请号：US11189765
申请日：2005-07-27
申请人： Yider Wu , Hiroyuki Ogawa , Unsoon Kim , Angela T. Hui
发明人： Yider Wu , Hiroyuki Ogawa , Unsoon Kim , Angela T. Hui
IPC分类号： H01L29/78
CPC分类号： H01L27/11524 , H01L21/28273 , H01L29/66825 , H01L29/66833
摘要： A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.
摘要翻译：提供了包括基板的存储器件。第一电介质层形成在衬底上。在衬底和第一介电层的一部分中形成隔离沟槽。在隔离沟槽的相对侧上的第一介电层上形成至少两个电荷存储元件。在所述至少两个电荷存储元件上形成第二电介质层。控制栅极层形成在第二介电层上，其中隔离沟槽具有适于减小电荷存储元件的交叉耦合噪声的宽度，并且其中至少两个电荷存储元件具有适于提供足够的栅极耦合的高度所述至少两个电荷存储元件和所述控制栅极层。

8. 发明授权

US07985687B1 System and method for improving reliability in a semiconductor device 有权
标题翻译：用于提高半导体器件的可靠性的系统和方法
公开(公告)号：US07985687B1
公开(公告)日：2011-07-26
申请号：US11186969
申请日：2005-07-22
申请人： Angela T. Hui , Hiroyuki Kinoshita , Unsoon Kim , Harpreet K. Sachar
发明人： Angela T. Hui , Hiroyuki Kinoshita , Unsoon Kim , Harpreet K. Sachar
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/28273 , H01L21/28282 , H01L21/3081 , H01L21/31111 , H01L21/76232 , H01L27/11521 , H01L27/11568
摘要： A method for forming a memory device includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.
摘要翻译：一种用于形成存储器件的方法包括在衬底上形成硬掩模，其中硬掩模包括形成在第一掩模层上的第一掩模层和第二掩模层。蚀刻衬底以形成沟槽。沟槽填充有场氧化物材料。使用第一蚀刻技术从存储器件剥离第二掩模层，并且使用第二蚀刻技术将第一掩模层从存储器件剥离，其中第二蚀刻技术不同于第一蚀刻技术。

9. 发明授权

US08076712B2 Semiconductor memory comprising dual charge storage nodes and methods for its fabrication 有权
标题翻译：半导体存储器包括双电荷存储节点及其制造方法
公开(公告)号：US08076712B2
公开(公告)日：2011-12-13
申请号：US12840165
申请日：2010-07-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
发明人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/42332 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
摘要翻译：提供了双电荷存储节点存储器件及其制造方法。在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。在第二部分上形成一层半导体材料。第一层状结构形成在电介质塞的第二部分的第一侧上，并且第二层结构形成在第二侧上，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层和第二电介质层。将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

10. 发明授权

US07767517B2 Semiconductor memory comprising dual charge storage nodes and methods for its fabrication 有权
标题翻译：半导体存储器包括双电荷存储节点及其制造方法
公开(公告)号：US07767517B2
公开(公告)日：2010-08-03
申请号：US11613513
申请日：2006-12-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
发明人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
IPC分类号： H01L21/8242
CPC分类号： H01L29/42332 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
摘要翻译：提供了双电荷存储节点存储器件及其制造方法。在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。在第二部分上形成一层半导体材料。第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层和第二电介质层。将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

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