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1. 发明申请

US20110289472A1 LAYOUT QUALITY EVALUATION 审中-公开
标题翻译：布局质量评估
公开(公告)号：US20110289472A1
公开(公告)日：2011-11-24
申请号：US12782926
申请日：2010-05-19
申请人： Ulrich A. Finkler , Mark A. Lavin , Amith Singhee
发明人： Ulrich A. Finkler , Mark A. Lavin , Amith Singhee
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for quantifying and improving layout quality of an IC is disclosed. The method includes receiving a drawn layout and placing essentially one dimensional measurement markers (chords) at various location in the drawn layout. This placement is done in such manner that contours of shapes in the drawn layout intersect a chord in at least two places. The length of the chord is defined as its portion delimited by the intersections, and a measurement of the chord is defined as obtaining its length. The drawn layout is subjected, with the exception of the chords, to a patterning simulation at a selected processing point. Following the simulation the chords are measured and the obtained lengths associated with the drawn layout and the processing point. The patterning simulation may be carried out at a variety processing points and the chord lengths following each simulation are associated with the respective processing point. The sets of lengths obtained at the various processing points are used to quantitatively evaluate the layout quality, to improve the layout quality and tune the processing window.
摘要翻译：公开了一种量化和提高IC布局质量的方法。该方法包括接收绘制的布局并且在绘制的布局中的各个位置放置基本上一维的测量标记（和弦）。这种放置以这样的方式完成，使得绘制布局中的形状的轮廓在至少两个地方与弦并行。弦的长度被定义为由交点限定的部分，并且弦的测量被定义为获得其长度。除了和弦之外，绘制的布局受到所选处理点处的图案化模拟的影响。在模拟之后，测量和弦并获得与绘制的布局和处理点相关联的长度。图案化模拟可以在各种处理点处执行，并且每个模拟之后的弦长与相应的处理点相关联。在各种处理点获得的长度集合用于定量评估布局质量，提高布局质量并调整处理窗口。

2. 发明申请

US20120167029A1 PHYSICAL DESIGN SYSTEM AND METHOD 失效
标题翻译：物理设计系统与方法
公开(公告)号：US20120167029A1
公开(公告)日：2012-06-28
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

3. 发明授权

US07823094B2 Pseudo-string based pattern recognition in L3GO designs 有权
标题翻译： L3GO设计中基于伪串的模式识别
公开(公告)号：US07823094B2
公开(公告)日：2010-10-26
申请号：US11621383
申请日：2007-01-09
申请人： Ulrich A. Finkler , Mark A. Lavin , Robert T. Sayah
发明人： Ulrich A. Finkler , Mark A. Lavin , Robert T. Sayah
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/504 , G06F2217/12 , Y02P90/265
摘要： A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a serialization system for converting an input region of glyph design data into a pseudo-string; and a pattern searching system that identifies matching patterns in the glyph design data by analyzing pseudo-strings generated by the serialization system. Pattern searching may include, e.g., predefined pattern searching and redundant pattern searching.
摘要翻译：一种用于处理与生成超大规模集成电路（VLSI）设计相关联的基于字形的数据的系统和方法。提供一种系统，其包括用于将字形设计数据的输入区域转换为伪字符串的串行化系统; 以及通过分析由串行化系统生成的伪串来识别字形设计数据中的匹配模式的模式搜索系统。模式搜索可以包括例如预定义模式搜索和冗余模式搜索。

4. 发明授权

US07536664B2 Physical design system and method 失效
标题翻译：物理设计系统及方法
公开(公告)号：US07536664B2
公开(公告)日：2009-05-19
申请号：US10917193
申请日：2004-08-12
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

5. 发明授权

US08473885B2 Physical design system and method 失效
公开(公告)号：US08473885B2
公开(公告)日：2013-06-25
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

6. 发明授权

US07814443B2 Graph-based pattern matching in L3GO designs 有权
标题翻译：基于图形的L3GO设计模式匹配
公开(公告)号：US07814443B2
公开(公告)日：2010-10-12
申请号：US11623541
申请日：2007-01-16
申请人： Ulrich A. Finkler , Mark A. Lavin , Robert T. Sayah
发明人： Ulrich A. Finkler , Mark A. Lavin , Robert T. Sayah
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a system for defining variable patterns using a pattern description language to create a glyph layout; and a graph-based pattern matching system that can identify potential matches amongst variable patterns in the glyph layout.
摘要翻译：一种用于处理与生成超大规模集成电路（VLSI）设计相关联的基于字形的数据的系统和方法。提供一种系统，其包括用于使用模式描述语言定义可变模式以创建字形布局的系统; 以及可以识别字形布局中的可变图案之间的潜在匹配的基于图形的模式匹配系统。

7. 发明申请

US20080172645A1 GRAPH-BASED PATTERN MATCHING IN L3GO DESIGNS 有权
标题翻译：在L3GO设计中基于图形的图案匹配
公开(公告)号：US20080172645A1
公开(公告)日：2008-07-17
申请号：US11623541
申请日：2007-01-16
申请人： Ulrich A. Finkler , Mark A. Lavin , Robert T. Sayah
发明人： Ulrich A. Finkler , Mark A. Lavin , Robert T. Sayah
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a system for defining variable patterns using a pattern description language to create a glyph layout; and a graph-based pattern matching system that can identify potential matches amongst variable patterns in the glyph layout.
摘要翻译：一种用于处理与生成超大规模集成电路（VLSI）设计相关联的基于字形的数据的系统和方法。提供一种系统，其包括用于使用模式描述语言定义可变模式以创建字形布局的系统; 以及可以识别字形布局中的可变图案之间的潜在匹配的基于图形的模式匹配系统。

8. 发明授权

US08219943B2 Physical design system and method 有权
标题翻译：物理设计系统及方法
公开(公告)号：US08219943B2
公开(公告)日：2012-07-10
申请号：US12425603
申请日：2009-04-17
申请人： John M Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50 , G06F19/00 , G03F1/00 , G21K5/00
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

9. 发明申请

US20090204930A1 IPHYSICAL DESIGN SYSTEM AND METHOD 有权
标题翻译：物理设计系统与方法
公开(公告)号：US20090204930A1
公开(公告)日：2009-08-13
申请号：US12425603
申请日：2009-04-17
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.
摘要翻译：一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。布局单元接收表示网格和字形格式的部分的电路描述。检查单元检查设计的网格和字形部分。精心设计单元从检查的设计生成目标布局。数据准备单元准备掩模制作的目标布局。模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

10. 发明申请

US20080165192A1 PSEUDO-STRING BASED PATTERN RECOGNITION IN L3GO DESIGNS 有权
标题翻译：基于PSEUDO-STRING的图案识别在L3GO设计中
公开(公告)号：US20080165192A1
公开(公告)日：2008-07-10
申请号：US11621383
申请日：2007-01-09
申请人： Ulrich A. Finkler , Mark A. Lavin , Robert T. Sayah
发明人： Ulrich A. Finkler , Mark A. Lavin , Robert T. Sayah
IPC分类号： G06T11/00
CPC分类号： G06F17/5068 , G06F17/504 , G06F2217/12 , Y02P90/265
摘要： A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a serialization system for converting an input region of glyph design data into a pseudo-string; and a pattern searching system that identifies matching patterns in the glyph design data by analyzing pseudo-strings generated by the serialization system. Pattern searching may include, e.g., predefined pattern searching and redundant pattern searching.
摘要翻译：一种用于处理与生成超大规模集成电路（VLSI）设计相关联的基于字形的数据的系统和方法。提供一种系统，其包括用于将字形设计数据的输入区域转换为伪字符串的序列化系统; 以及通过分析由串行化系统生成的伪串来识别字形设计数据中的匹配模式的模式搜索系统。模式搜索可以包括例如预定义模式搜索和冗余模式搜索。

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