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    • 4. 发明申请
    • METHOD AND APPARATUS FOR BANDWIDTH EFFICIENT AND BOUNDED LATENCY PACKET BUFFERING
    • 用于带宽效率和边界的延迟分组缓冲的方法和装置
    • WO2007004159A3
    • 2008-01-03
    • PCT/IB2006052182
    • 2006-06-29
    • UTSTARCOM INCSINGH KANWAR JITKUMAR DHIRAJ
    • SINGH KANWAR JITKUMAR DHIRAJ
    • G06F12/00G06F13/00G06F13/28
    • G06F13/4059
    • A system and method for buffering data packets in a data network device having a DRAM buffer are presented. When writing packets, the buffering system separates available memory channels into two groups corresponding to ingress and egress data. Based on the source of the data packets, data pages from the data packets are assigned to channels from either the ingress or egress group. Non-conflicting sets of addresses, called cachelines, are requested on each memory channel, and the data pages are evenly distributed over the assigned channels before being mapped to a cacheline. The number of read transactions currently being monitored by the system is controlled in order to reduce random packet read conflicts. Additionally, write and read transactions are grouped by an arbitration unit prior to being sent to the DRAM controller.
    • 提出了一种用于在具有DRAM缓冲器的数据网络设备中缓冲数据分组的系统和方法。 当写入数据包时,缓冲系统将可用存储器通道分为两个对应于入口和出口数据的组。 基于数据包的来源,来自数据包的数据页被分配给来自入口或出口组的信道。 在每个存储器通道上请求非冲突的地址集合,称为高速缓存线,并且数据页在映射到高速缓存线之前均匀分布在所分配的通道上。 控制系统当前正在监视的读取事务的数量,以便减少随机数据包读取冲突。 此外,写入和读取事务在发送到DRAM控制器之前由仲裁单元分组。