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1. 发明授权

US08283709B2 Semiconductor structure 有权
标题翻译：半导体结构
公开(公告)号：US08283709B2
公开(公告)日：2012-10-09
申请号：US12899721
申请日：2010-10-07
申请人： Tzung Han Lee , Chung-Lin Huang , Hsien-Wen Liu
发明人： Tzung Han Lee , Chung-Lin Huang , Hsien-Wen Liu
IPC分类号： H01L29/772
CPC分类号： H01L21/76224 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/78
摘要： A semiconductor device is disclosed which includes a silicide substrate, a nitride layer, two STIs, and a strain nitride. The silicide substrate has two doping areas. The nitride layer is deposited on the silicide substrate. The silicide substrate and the nitride layer have a recess running through. The two doping areas are at two sides of the recess. The end of the recess has an etching space bigger than the recess. The top of the silicide substrate has a fin-shaped structure. The two STIs are at the two opposite sides of the silicide substrate (recess). The strain nitride is spacer-formed in the recess and attached to the side wall of the silicide substrate, nitride layer, two STIs. The two doping areas cover the strain nitride. As a result, the efficiency of semiconductor is improved, and the drive current is increased.
摘要翻译：公开了一种半导体器件，其包括硅化物衬底，氮化物层，两个STI和应变氮化物。硅化物衬底具有两个掺杂区域。氮化物层沉积在硅化物衬底上。硅化物衬底和氮化物层具有贯穿的凹槽。两个掺杂区位于凹槽的两侧。凹部的端部具有比凹部大的蚀刻空间。硅化物衬底的顶部具有鳍状结构。两个STI位于硅化物衬底（凹槽）的两个相对侧。应变氮化物在凹槽中间隔形成并附着到硅化物衬底，氮化物层，两个STI的侧壁上。两个掺杂区域覆盖了应变氮化物。结果，提高了半导体的效率，并且提高了驱动电流。

2. 发明授权

US08431933B2 Memory layout structure and memory structure 有权
标题翻译：内存布局结构和内存结构
公开(公告)号：US08431933B2
公开(公告)日：2013-04-30
申请号：US12874232
申请日：2010-09-02
申请人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
发明人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
IPC分类号： H01L29/10
CPC分类号： H01L29/4983 , H01L27/0207 , H01L27/10855 , H01L27/10876 , H01L27/10882 , H01L29/4236
摘要： A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.
摘要翻译：公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸（边缘壁），以执行侧壁接触。自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

3. 发明申请

US20120012907A1 Memory layout structure and memory structure 有权
标题翻译：内存布局结构和内存结构
公开(公告)号：US20120012907A1
公开(公告)日：2012-01-19
申请号：US12874232
申请日：2010-09-02
申请人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
发明人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
IPC分类号： H01L27/108
CPC分类号： H01L29/4983 , H01L27/0207 , H01L27/10855 , H01L27/10876 , H01L27/10882 , H01L29/4236
摘要： A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.
摘要翻译：公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸（边缘壁），以执行侧壁接触。自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

4. 发明申请

US20130146954A1 Method Of Memory Array And Structure Form 审中-公开
标题翻译：存储器阵列和结构形式的方法
公开(公告)号：US20130146954A1
公开(公告)日：2013-06-13
申请号：US13429448
申请日：2012-03-26
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/0207 , H01L27/10876 , H01L27/10885
摘要： The present invention provides a memory array including a substrate, an isolation region, a plurality of active regions, a plurality of buried bit lines, a plurality of word lines, a plurality of drain regions and a plurality of capacitors. The isolation region and the active regions are disposed in the substrate and the active regions are encompassed and isolated by the isolation region. The buried bit lines are disposed in the substrate and extend in the second direction. The word lines are disposed in the substrate extend in the first direction. The drain regions are disposed in the active region not covered by the word lines. The capacitors are disposed on the substrate and electrically connected to the drain regions.
摘要翻译：本发明提供了一种存储器阵列，其包括衬底，隔离区，多个有源区，多个掩埋位线，多个字线，多个漏极区和多个电容。隔离区域和有源区域设置在衬底中，并且有源区域被隔离区域包围和隔离。掩埋位线设置在基板中并沿第二方向延伸。字线设置在基板中沿第一方向延伸。漏极区域设置在未被字线覆盖的有源区域中。电容器设置在基板上并电连接到漏极区域。

5. 发明授权

US07960241B2 Manufacturing method for double-side capacitor of stack DRAM 有权
标题翻译：堆叠DRAM双面电容器制造方法
公开(公告)号：US07960241B2
公开(公告)日：2011-06-14
申请号：US12698322
申请日：2010-02-02
申请人： Shin-Bin Huang , Tzung-Han Lee , Chung-Lin Huang
发明人： Shin-Bin Huang , Tzung-Han Lee , Chung-Lin Huang
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L28/90
摘要： A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors.
摘要翻译：堆叠DRAM的双面电容器的制造方法具有以下步骤：在隔离沟槽和电容器沟槽中形成牺牲结构; 在所述牺牲结构上形成第一覆盖层和第二覆盖层; 修改第二覆盖层的一部分; 去除未改性的第二覆盖层和第一覆盖层以暴露牺牲结构; 去除所述牺牲结构的暴露部分以暴露所述电极层; 去除暴露的电极层以暴露氧化物层; 并去除氧化物层和牺牲结构以形成双面电容器。

6. 发明授权

US08779494B2 High-k metal gate random access memory 有权
标题翻译：高k金属门随机存取存储器
公开(公告)号：US08779494B2
公开(公告)日：2014-07-15
申请号：US13426825
申请日：2012-03-22
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron-Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron-Fu Chu
IPC分类号： H01L29/94
CPC分类号： H01L27/10873 , H01L27/10885 , H01L27/10891
摘要： The instant disclosure relates to a high-k metal gate random access memory. The memory includes a substrate, a plurality of bit line units, source regions, gate structures, drain regions, word line units, and capacitance units. The substrate has a plurality of trenches, and the bit line units are arranged on the substrate. The source regions are disposed on the bit line units, and the gate structures are disposed on the source regions. Each gate structure has a metal gate and a channel area formed therein. The gate structures are topped with the drain regions. The word lines units are arranged between the source and drain regions. The capacitance units are disposed on the drain regions. Another memory is also disclosed, where each drain region and a portion of each gate structure are disposed in the respective capacitance unit, with the drain region being a lower electrode layer.
摘要翻译：本公开涉及高k金属栅极随机存取存储器。存储器包括衬底，多个位线单元，源极区，栅极结构，漏极区，字线单元和电容单元。衬底具有多个沟槽，并且位线单元布置在衬底上。源极区域设置在位线单元上，栅极结构设置在源极区域上。每个栅极结构具有形成在其中的金属栅极和沟道区域。栅极结构顶部带有漏极区域。字线单元布置在源区和漏区之间。电容单元设置在漏极区域上。还公开了另一种存储器，其中每个漏极区域和每个栅极结构的一部分设置在相应的电容单元中，漏极区域是下部电极层。

7. 发明授权

US08703562B2 Manufacturing method of random access memory 有权
标题翻译：随机存取存储器的制造方法
公开(公告)号：US08703562B2
公开(公告)日：2014-04-22
申请号：US13426832
申请日：2012-03-22
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron-Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron-Fu Chu
IPC分类号： H01L21/8238
CPC分类号： H01L27/10894 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： A manufacturing method of a random access memory includes the following steps: providing a semiconductor structure having an array region and a peripheral region; forming a plurality of first trenches in the array region, and concurrently, a plurality of second trenches on the peripheral region; forming a polysilicon layer to cover the array region and the peripheral region, and the first and the second trenches are filled up with the polysilicon layer; planarizing the polysilicon layer so the remaining polysilicon layer only resides in the first and the second trenches; forming a conductive layer on the semiconductor structure; patterning the conductive layer to form a plurality of landing pads on the array region, and a plurality of bit line units on the peripheral region; and forming a plurality of capacitor units which is in electrical connection to the landing pads.
摘要翻译：随机存取存储器的制造方法包括以下步骤：提供具有阵列区域和周边区域的半导体结构; 在阵列区域中形成多个第一沟槽，同时在周边区域上形成多个第二沟槽; 形成多晶硅层以覆盖阵列区域和外围区域，并且第一和第二沟槽被多晶硅层填充; 平坦化多晶硅层，使得剩余的多晶硅层仅驻留在第一和第二沟槽中; 在半导体结构上形成导电层; 图案化导电层以在阵列区域上形成多个着陆焊盘，以及在周边区域上形成多个位线单元; 以及形成与所述着陆焊盘电连接的多个电容器单元。

8. 发明申请

US20130119448A1 MEMORY LAYOUT STRUCTURE AND MEMORY STRUCTURE 有权
标题翻译：存储器布局结构和存储器结构
公开(公告)号：US20130119448A1
公开(公告)日：2013-05-16
申请号：US13343668
申请日：2012-01-04
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
IPC分类号： H01L27/108
CPC分类号： H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10891 , H01L28/90
摘要： A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each first doped region is disposed in a middle region; a plurality of second doped region, wherein each second doped region is disposed in a distal end region respectively; a plurality of recessed gate structures; a plurality of word lines electrically connected to each recessed gate structure respectively; a plurality of digit lines electrically connected to the first doped region respectively; and a plurality of capacitors electrically connected to each second doped region respectively.
摘要翻译：存储器阵列布局包括具有多个有源区域的有源区域阵列，其中有源区域沿着第二方向交替布置，并且相邻有源区域的一部分侧沿第二方向重叠; 多个第一掺杂区域，其中每个第一掺杂区域设置在中间区域中; 多个第二掺杂区域，其中每个第二掺杂区域分别设置在远端区域中; 多个凹入栅结构; 分别电连接到每个凹入栅结构的多个字线; 分别电连接到第一掺杂区的多个数字线; 以及分别与每个第二掺杂区域电连接的多个电容器。

9. 发明申请

US20130052786A1 FABRICATING METHOD OF DRAM STRUCTURE 有权
标题翻译： DRAM结构的制作方法
公开(公告)号：US20130052786A1
公开(公告)日：2013-02-28
申请号：US13297276
申请日：2011-11-16
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
IPC分类号： H01L21/02
CPC分类号： H01L27/10894 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L29/66545
摘要： A fabricating method of a DRAM structure includes providing a substrate comprising a memory array region and a peripheral region. A buried gate transistor is disposed within the memory array region, and a planar gate transistor is disposed within the peripheral region. Furthermore, an interlayer dielectric layer covers the memory array region, the buried gate transistor and the planar gate transistor. Then, a capping layer of the planar gate transistor and part of the interlayer dielectric layer are removed simultaneously so that a first contact hole, a second contact hole and a third contact hole are formed in the interlayer dielectric layer. A drain doping region of the buried gate transistor is exposed through the first contact hole, a doping region of the planar gate transistor is exposed through the second contact hole, and a gate electrode of the planar gate transistor is exposed through the third contact hole.
摘要翻译： DRAM结构的制造方法包括提供包括存储器阵列区域和外围区域的衬底。掩埋栅极晶体管设置在存储器阵列区域内，并且平面栅极晶体管设置在周边区域内。此外，层间电介质层覆盖存储器阵列区域，掩埋栅极晶体管和平面栅极晶体管。然后，同时去除平面栅晶体管的覆盖层和层间电介质层的一部分，使得在层间电介质层中形成第一接触孔，第二接触孔和第三接触孔。埋入栅极晶体管的漏极掺杂区域通过第一接触孔露出，平面栅极晶体管的掺杂区域通过第二接触孔露出，平面栅极晶体管的栅电极通过第三接触孔露出。

10. 发明授权

US08330198B2 Device for preventing current-leakage 有权
标题翻译：防止漏电的装置
公开(公告)号：US08330198B2
公开(公告)日：2012-12-11
申请号：US12758252
申请日：2010-04-12
申请人： Shin Bin Huang , Chung-Lin Huang , Ching-Nan Hsiao , Tzung Han Lee
发明人： Shin Bin Huang , Chung-Lin Huang , Ching-Nan Hsiao , Tzung Han Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/0259
摘要： A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem.
摘要翻译：用于防止漏电的装置位于存储单元的晶体管和电容器之间。用于防止漏电的装置的两个端子分别与晶体管的从端和电容器的电极连接。用于防止漏电的装置具有至少两个p-n结。用于防止漏电的装置是侧向可控硅整流器，用于交流电流的二极管或可控硅整流器。通过利用用于防止漏电的装置的驱动特性，存储在电容器中的电荷几乎不会通过用于防止晶体管截止时漏电的装置，从而改善漏电问题。

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