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1. 发明授权

US6060349A Planarization on an embedded dynamic random access memory 失效
标题翻译：嵌入式动态随机存取存储器的平面化
公开(公告)号：US6060349A
公开(公告)日：2000-05-09
申请号：US152449
申请日：1998-09-14
申请人： Tzu-Min Peng , Keh-Ching Huang , Tung-Po Chen , Tz-Guei Jung
发明人： Tzu-Min Peng , Keh-Ching Huang , Tung-Po Chen , Tz-Guei Jung
IPC分类号： H01L21/8242
CPC分类号： H01L27/10844 , H01L27/10852
摘要： A planarization method used in fabricating an embedded dynamic random access memory (DRAM). After a number of metal-oxide semiconductor (MOS) transistors and a number of capacitors are formed on a semiconductor substrate, a first inter-layer di-electric (ILD) layer is formed over the substrate. The embedded DRAM is divided into a memory region and a logic region. Next, planarization is performed. A dummy metal layer is formed and coupled to an interchangeable source/drain region of the MOS transistor in the logic region. Then a second ILD layer is formed over the logic region to compensate difference in height between the logic region and the memory region. Then, a via hole/plug is formed in the logic region to extend the first metal layer. A second metal layer with required contact window/plugs is formed over the substrate.
摘要翻译：用于制造嵌入式动态随机存取存储器（DRAM）的平面化方法。在半导体衬底上形成多个金属氧化物半导体（MOS）晶体管和多个电容器之后，在衬底上形成第一层间二电极（ILD）层。嵌入式DRAM被分成存储区域和逻辑区域。接下来，进行平坦化。形成虚设的金属层并与逻辑区域中的MOS晶体管的可互换的源/漏区耦合。然后在逻辑区域上形成第二ILD层以补偿逻辑区域和存储区域之间的高度差异。然后，在逻辑区域中形成通孔/插头以延伸第一金属层。在衬底上形成具有所需接触窗/插塞的第二金属层。

2. 发明授权

US06218239B1 Manufacturing method of a bottom plate 失效
标题翻译：底板的制造方法
公开(公告)号：US06218239B1
公开(公告)日：2001-04-17
申请号：US09195168
申请日：1998-11-17
申请人： Keh-Ching Huang , Wen-Jeng Lin , Tz-Guei Jung , Jacob Chen
发明人： Keh-Ching Huang , Wen-Jeng Lin , Tz-Guei Jung , Jacob Chen
IPC分类号： H01L218242
CPC分类号： H01L28/87 , H01L27/10855 , H01L28/91
摘要： The invention provides a manufacturing method of forming a bottom plate for a capacitor on a substrate, wherein the substrate comprises a MOS transistor having a gate and a pair of source/drain regions. A crown-liked conductive plate is formed over an insulation oxide layer and a contact plug. The crown-liked conductive plate penetrates the insulation layer and the stop layer, wherein the bottom of the crown-like conductive plate is electrically connected to the contact plug. The crown-like conductive plate, served as the bottom plate for a DRAM capacitor, is composed of tungsten silicide or a combination of a tungsten nitride layer and a tungsten layer.
摘要翻译：本发明提供一种在基板上形成用于电容器的底板的制造方法，其中所述基板包括具有栅极和一对源极/漏极区域的MOS晶体管。冠状导电板形成在绝缘氧化物层和接触插塞上。冠状导电板穿透绝缘层和阻挡层，其中冠状导电板的底部电连接到接触插塞。用作DRAM电容器的底板的冠状导电板由硅化钨或氮化钨层和钨层的组合构成。

3. 发明授权

US06187674B1 Manufacturing method capable of preventing corrosion and contamination of MOS gate 失效
标题翻译：能够防止MOS栅的腐蚀和污染的制造方法
公开(公告)号：US06187674B1
公开(公告)日：2001-02-13
申请号：US09208605
申请日：1998-12-08
申请人： Tung-Po Chen , Yung-Chang Lin , Keh-Ching Huang , Jacob Chen
发明人： Tung-Po Chen , Yung-Chang Lin , Keh-Ching Huang , Jacob Chen
IPC分类号： H01L2144
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/28247 , H01L29/4941
摘要： A MOS gate manufacturing operation is capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate. The thin oxide layer is capable of protecting the barrier layer against acid corrosion without causing any noticeable increase in gate conductivity.
摘要翻译： MOS门制造操作能够防止酸腐蚀和车站污染。该制造方法包括以下步骤：在硅衬底上顺序地形成多晶硅层，阻挡层，硅化物层和覆盖层，然后蚀刻以形成栅极结构。接下来，进行快速热处理以在阻挡层的暴露的侧壁上形成氧化物层。最后，通过在栅极的每一侧上形成具有轻掺杂漏极结构的源极/漏极区域来清洁衬底。薄氧化物层能够保护阻挡层免受酸腐蚀，而不会导致栅极导电性的任何明显增加。

4. 发明授权

US06316311B1 Method of forming borderless contact 失效
标题翻译：形成无边界接触的方法
公开(公告)号：US06316311B1
公开(公告)日：2001-11-13
申请号：US09203036
申请日：1998-12-01
申请人： Tung-Po Chen , Tong-Yu Chen , Keh-Ching Huang , Jacob Chen
发明人： Tung-Po Chen , Tong-Yu Chen , Keh-Ching Huang , Jacob Chen
IPC分类号： H01L218242
CPC分类号： H01L21/76897 , H01L27/10873 , H01L27/10894
摘要： A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the logic region. The MOS transistor comprises a gate, a source/drain region and a cap insulating layer on the gate. An etching stop layer is formed on the substrate to cover the MSO transistor and the STI structure. A dielectric layer is formed in the etching stop layer. The dielectric layer, the etching stop layer and the cap insulating layer are partially removed to form a first opening according to the pattern of a first mask layer. The first opening exposes the gate. According to the pattern of a second mask layer, the dielectric layer and the etching stop layer are partially removed to form openings, which expose the source/drain region, in the dielectric layer.
摘要翻译：提供了形成无边界接触的方法。提供基板。衬底至少具有逻辑区域和存储区域。在逻辑区域上形成MOS晶体管和STI结构。 MOS晶体管包括栅极，源极/漏极区域和栅极上的帽绝缘层。在衬底上形成蚀刻停止层以覆盖MSO晶体管和STI结构。在蚀刻停止层中形成介电层。根据第一掩模层的图案，介电层，蚀刻停止层和盖绝缘层被部分去除以形成第一开口。第一个开放暴露了大门。根据第二掩模层的图案，电介质层和蚀刻停止层被部分地去除以形成在电介质层中暴露源/漏区的开口。

5. 发明授权

US6107131A Method of fabricating interpoly dielectric layer of embedded dynamic random access memory 失效
标题翻译：嵌入式动态随机存取存储器的多层电介质层的制作方法
公开(公告)号：US6107131A
公开(公告)日：2000-08-22
申请号：US73981
申请日：1998-05-07
申请人： Keh-Ching Huang
发明人： Keh-Ching Huang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10873 , H01L27/10894
摘要： A method of fabricating an interpoly dielectric layer of an embedded DRAM wherein a substrate having a logic FET is provided and the logic FET has a source/drain region where a titanium suicide layer is formed thereon. An oxide layer is formed on the substrate and a silicion nitride layer is formed by PECVD on the oxide layer. The thermal stability can be improved because the formation of the compressive silicon nitride layer and the oxide layer prevents junction leakage, which is produced from the embedded DRAM.
摘要翻译：一种制造嵌入式DRAM的间隔电介质层的方法，其中提供具有逻辑FET的衬底，并且逻辑FET具有在其上形成硅化钛层的源极/漏极区域。在衬底上形成氧化物层，在氧化物层上通过PECVD形成硅氮化物层。由于形成压缩氮化硅层和氧化物层可防止从嵌入式DRAM产生的结漏电，因此可以提高热稳定性。

6. 发明授权

US6010968A Method for forming a contact opening with multilevel etching 有权
标题翻译：用多层蚀刻形成接触孔的方法
公开(公告)号：US6010968A
公开(公告)日：2000-01-04
申请号：US220541
申请日：1998-12-24
申请人： Chan-Lon Yang , Tong-Yu Chen , Keh-Ching Huang
发明人： Chan-Lon Yang , Tong-Yu Chen , Keh-Ching Huang
IPC分类号： H01L21/311 , H01L21/00
CPC分类号： H01L21/31116
摘要： A multilevel contact etching method to form a contact opening is provided. The method contains using an inductively coupled plasma (ICP) etcher to produce a high plasma density condition. The plasma gas etchant is composed of C.sub.4 F.sub.8 /CH.sub.2 F.sub.2 /CO/Ar with a ratio of 3:4:12:80 so that silicon nitride can be selectively etched while the silicon and silicide are not etched. Each content ratio of the plasma gas etchant allows a variance of about 20%. Wall temperature of the ICP etcher is about 100.degree. C.-300.degree. C. A cooling system for a wafer pad is about -20.degree. C.-20.degree. C. Chamber pressure is about 5-100 mtorr. Bias power on the wafer pad is about 1000 W-3000 W. Source power of an inductance coil is about 500 W-3000 W.
摘要翻译：提供了形成接触开口的多层接触蚀刻方法。该方法包括使用电感耦合等离子体（ICP）蚀刻器来产生高等离子体密度条件。等离子体气体蚀刻剂由比例为3：4：12：80的C4F8 / CH2F2 / CO / Ar组成，以便在不蚀刻硅和硅化物的情况下，可以选择性地蚀刻氮化硅。等离子体气体蚀刻剂的每个含量比允许约20％的变化。 ICP蚀刻器的壁温为约100℃-300℃。晶片垫的冷却系统为约-20℃-20℃。室压力为约5-100mtorr。晶片垫上的偏置功率约为1000W-3000W。电感线圈的功率为约500W-3000W。

7. 发明授权

US06306757B1 Method for forming a multilevel interconnect 失效
标题翻译：用于形成多层互连的方法
公开(公告)号：US06306757B1
公开(公告)日：2001-10-23
申请号：US09323890
申请日：1999-06-02
申请人： Keh-Ching Huang , Ming-Sheng Yang , Tong-Yu Chen , Tzu-Guey Jung
发明人： Keh-Ching Huang , Ming-Sheng Yang , Tong-Yu Chen , Tzu-Guey Jung
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76841 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A metallization method for forming multilevel interconnect is disclosed. The method includes firstly providing a first conductor layer on which there is a dielectric layer. A glue layer is then formed on the dielectric layer, followed by forming an opening from top surface of the glue layer to the first conductor layer. After forming a barrier layer on the glue layer and all surfaces in the opening, a second conductor is formed on the barrier layer and fills the opening. Subsequently, the second conductor layer and the barrier layer are removed until the glue layer exposes. A third conductor is defined on the glue layer and the second conductor. The product will solve the problem of high via resistivity caused by stripping solvent and etchant.
摘要翻译：公开了一种用于形成多层互连的金属化方法。该方法包括首先提供其上存在电介质层的第一导体层。然后在电介质层上形成胶层，随后从胶层的顶表面到第一导体层形成开口。在胶层和开口中的所有表面上形成阻挡层之后，在阻挡层上形成第二导体并填充开口。随后，去除第二导体层和阻挡层，直到胶层露出。第三导体被限定在胶层和第二导体上。该产品将解决由剥离溶剂和蚀刻剂引起的高电阻率的问题。

8. 发明授权

US06184147B2 Method for forming a high aspect ratio borderless contact hole 有权
标题翻译：用于形成高纵横比无边界接触孔的方法
公开(公告)号：US06184147B2
公开(公告)日：2001-02-06
申请号：US09263421
申请日：1999-03-05
申请人： Chan-Lon Yang , Tong-Yu Chen , Keh-Ching Huang
发明人： Chan-Lon Yang , Tong-Yu Chen , Keh-Ching Huang
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01J37/32082 , H01J2237/3347 , H01L21/31116 , H01L21/31144 , H01L21/76802
摘要： A method for forming a high aspect ration (HAR>4:1) borderless contact hole is described. The method forms a contact/via hole in the silicon oxide layer by performing an etching process with an etchant, C4F8/C2F6,/Ar/CO or C4F8/Ar/CO, on an etcher. The etcher includes a ring, a roof, a chiller and a chamber. The etchant used in the etching process is controlled under conditions including a C4F8 flow of about 10 to 20 sccm, a CO flow of about 1 to 100 sccm, and an Ar flow of about 100 to 500 sccm. The flow of C2F6 is about 0.5 to 1.5 times that of C4F8. The conditions of the etcher include a roof temperature of about 150 to 300° C., a chiller temperature of about −20 to 20° C., a wall temperature of about 150 to 400° C., a ring temperature of about 150 to 400° C., and a pressure within the chamber of about 4 to 50 mtorr. By controlling the chamber pressure and the deposition rate of the polymer molecules, a properly profiled contact hole is obtained.
摘要翻译：描述了形成高纵横比（HAR> 4:1）无边界接触孔的方法。该方法通过在蚀刻剂上用蚀刻剂C 4 F 8 / C 2 F 6，/ Ar / CO或C 4 F 8 / Ar / CO执行蚀刻处理来形成氧化硅层中的接触/通孔。蚀刻器包括环，屋顶，冷却器和室。在蚀刻工艺中使用的蚀刻剂在约10至20sccm的C 4 F 8流量，约1至100sccm的CO流量和约100至500sccm的Ar流量的条件下进行控制。 C2F6的流量约为C4F8的0.5〜1.5倍。蚀刻器的条件包括约150至300℃的屋顶温度，约-20至20℃的冷却器温度，约150至400℃的壁温度，约150至400℃的环境温度 400℃，室内的压力为约4至50毫托。通过控制室压力和聚合物分子的沉积速率，获得适当的异型接触孔。

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