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1. 发明授权

US08178407B2 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US08178407B2
公开(公告)日：2012-05-15
申请号：US12561395
申请日：2009-09-17
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

2. 发明申请

US20070161193A1 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US20070161193A1
公开(公告)日：2007-07-12
申请号：US11327792
申请日：2006-01-06
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

3. 发明申请

US20100009504A1 SYSTEMS AND METHODS FOR A HIGH DENSITY, COMPACT MEMORY ARRAY 有权
标题翻译：高密度，紧密记忆阵列的系统和方法
公开(公告)号：US20100009504A1
公开(公告)日：2010-01-14
申请号：US12561395
申请日：2009-09-17
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

4. 发明授权

US07608886B2 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US07608886B2
公开(公告)日：2009-10-27
申请号：US11327792
申请日：2006-01-06
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个电池的位数，并实现更高密度的存储器阵列。

5. 发明申请

US20100290293A1 METHOD OF IDENTIFYING LOGICAL INFORMATION IN A PROGRAMMING AND ERASING CELL BY ON-SIDE READING SCHEME 审中-公开
标题翻译：通过边界读取方案识别编程和擦除单元中的逻辑信息的方法
公开(公告)号：US20100290293A1
公开(公告)日：2010-11-18
申请号：US12845064
申请日：2010-07-28
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.
摘要翻译：公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

6. 发明授权

US07495967B2 Method of identifying logical information in a programming and erasing cell by on-side reading scheme 有权
标题翻译：通过旁路读取方案识别编程和擦除单元中的逻辑信息的方法
公开(公告)号：US07495967B2
公开(公告)日：2009-02-24
申请号：US11601710
申请日：2006-11-20
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.
摘要翻译：公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

7. 发明申请

US20050124116A1 3D polysilicon ROM and method of fabrication thereof 有权
标题翻译： 3D多晶硅ROM及其制造方法
公开(公告)号：US20050124116A1
公开(公告)日：2005-06-09
申请号：US10728767
申请日：2003-12-08
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Hsiang-Lan Lung , Chao-I Wu
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Hsiang-Lan Lung , Chao-I Wu
IPC分类号： H01L21/336 , H01L27/06 , H01L31/113
CPC分类号： H01L27/0688
摘要： A 3D polysilicon read only memory at least including: a silicon substrate, an isolated silicon dioxide (SiO2) layer, a N-Type heavily doped (N+) polysilicon layer, a first oxide layer, a dielectric layer, a P-Type lightly doped (P−) polysilicon layer, at least a neck structure, and a second oxide layer. The isolated SiO2 layer is deposited on the silicon substrate, and the N+ polysilicon layer is deposited on the isolated SiO2 layer. The N+ polysilicon layer is further defined a plurality of parallel, separate word lines (WL), and the first oxide layer is filled in the space between the word lines. The dielectric layer is deposited on the word lines and the first oxide layer. The P-Type lightly doped (P−) polysilicon layer is deposited on the dielectric layer and is further defined a plurality of parallel, separate bit lines (BL). The bit lines overlap the word lines, from a top view, to form a shape approximately as a cross. There are at least a neck structure individually formed between the first polysilicon layer and the second polysilicon layer by isotropy wet etching the dielectric layer, with using dilute hydrofluoric acid (HF) as the example. The second oxide layer is filled in the space between the bit lines and is on the word lines and the first oxide layer.
摘要翻译：至少包括硅衬底，隔离二氧化硅（SiO 2）层，N型重掺杂（N +）多晶硅层，第一氧化物层，电介质层，P型轻掺杂（P）多晶硅层，至少颈部结构和第二氧化物层。隔离的SiO 2层沉积在硅衬底上，并且N +多晶硅层沉积在隔离的SiO 2层上。 N +多晶硅层进一步限定多个平行的单独的字线（WL），并且第一氧化物层被填充在字线之间的空间中。介电层沉积在字线和第一氧化物层上。 P型轻掺杂（P）多晶硅层沉积在电介质层上，并进一步限定多个平行的分开的位线（BL）。位线从顶视图与字线重叠，以形成大致为十字形的形状。通过使用稀氢氟酸（HF）作为实例，通过各向同性湿蚀刻介电层，至少在第一多晶硅层和第二多晶硅层之间形成颈部结构。第二氧化物层填充在位线之间的空间中，并且位于字线和第一氧化物层上。

8. 发明申请

US20090101966A1 Method of identifying logical information in a programming and erasing cell by on-side reading scheme 有权
公开(公告)号：US20090101966A1
公开(公告)日：2009-04-23
申请号：US12314881
申请日：2008-12-18
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： H01L29/792
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

9. 发明申请

US20080084762A1 Method of identifying logical information in a programming and erasing cell by on-side reading scheme 有权
标题翻译：通过旁路读取方案识别编程和擦除单元中的逻辑信息的方法
公开(公告)号：US20080084762A1
公开(公告)日：2008-04-10
申请号：US11601710
申请日：2006-11-20
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.
摘要翻译：公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

10. 发明授权

US07085168B2 Programming method for controlling memory threshold voltage distribution 有权
标题翻译：用于控制存储器阈值电压分布的编程方法
公开(公告)号：US07085168B2
公开(公告)日：2006-08-01
申请号：US11026799
申请日：2004-12-30
申请人： Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
发明人： Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
IPC分类号： G11C16/34
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/12 , G11C16/3459 , G11C16/3481
摘要： A method for programming one or more memory cells is disclosed. The one or more memory cells need to be two sides operated. After verifying both sides of each memory cell to identify the sides of the memory cells to be programmed, a programming voltage pulse is given to the first sides of the memory cells identified to be programmed. Another verification process is performed for both sides of each memory cell to identify the sides of the memory cells to be programmed. Next, a programming voltage pulse is given to the second sides of the memory cells identified to be programmed. The verifying both sides, programming the first sides, verifying both sides, and programming the second sides will continue until the both sides of each memory cell are programmed to a target programming voltage. The target programming voltage might have multiple voltage levels.
摘要翻译：公开了一种用于编程一个或多个存储器单元的方法。一个或多个存储单元需要是双面操作的。在验证每个存储器单元的两侧以识别待编程的存储器单元的侧面之后，向被识别为被编程的存储器单元的第一侧提供编程电压脉冲。对每个存储单元的两侧执行另一个验证过程，以识别待编程的存储器单元的侧面。接下来，将编程电压脉冲提供给被识别为被编程的存储器单元的第二侧。验证两侧，编程第一面，验证双面，并对第二面进行编程将一直持续到每个存储单元的两侧都编程为目标编程电压。目标编程电压可能有多个电压电平。

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