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1. 发明申请

US20050124116A1 3D polysilicon ROM and method of fabrication thereof 有权
标题翻译： 3D多晶硅ROM及其制造方法
公开(公告)号：US20050124116A1
公开(公告)日：2005-06-09
申请号：US10728767
申请日：2003-12-08
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Hsiang-Lan Lung , Chao-I Wu
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Hsiang-Lan Lung , Chao-I Wu
IPC分类号： H01L21/336 , H01L27/06 , H01L31/113
CPC分类号： H01L27/0688
摘要： A 3D polysilicon read only memory at least including: a silicon substrate, an isolated silicon dioxide (SiO2) layer, a N-Type heavily doped (N+) polysilicon layer, a first oxide layer, a dielectric layer, a P-Type lightly doped (P−) polysilicon layer, at least a neck structure, and a second oxide layer. The isolated SiO2 layer is deposited on the silicon substrate, and the N+ polysilicon layer is deposited on the isolated SiO2 layer. The N+ polysilicon layer is further defined a plurality of parallel, separate word lines (WL), and the first oxide layer is filled in the space between the word lines. The dielectric layer is deposited on the word lines and the first oxide layer. The P-Type lightly doped (P−) polysilicon layer is deposited on the dielectric layer and is further defined a plurality of parallel, separate bit lines (BL). The bit lines overlap the word lines, from a top view, to form a shape approximately as a cross. There are at least a neck structure individually formed between the first polysilicon layer and the second polysilicon layer by isotropy wet etching the dielectric layer, with using dilute hydrofluoric acid (HF) as the example. The second oxide layer is filled in the space between the bit lines and is on the word lines and the first oxide layer.
摘要翻译：至少包括硅衬底，隔离二氧化硅（SiO 2）层，N型重掺杂（N +）多晶硅层，第一氧化物层，电介质层，P型轻掺杂（P）多晶硅层，至少颈部结构和第二氧化物层。隔离的SiO 2层沉积在硅衬底上，并且N +多晶硅层沉积在隔离的SiO 2层上。 N +多晶硅层进一步限定多个平行的单独的字线（WL），并且第一氧化物层被填充在字线之间的空间中。介电层沉积在字线和第一氧化物层上。 P型轻掺杂（P）多晶硅层沉积在电介质层上，并进一步限定多个平行的分开的位线（BL）。位线从顶视图与字线重叠，以形成大致为十字形的形状。通过使用稀氢氟酸（HF）作为实例，通过各向同性湿蚀刻介电层，至少在第一多晶硅层和第二多晶硅层之间形成颈部结构。第二氧化物层填充在位线之间的空间中，并且位于字线和第一氧化物层上。

2. 发明授权

US06952038B2 3D polysilicon ROM and method of fabrication thereof 有权
标题翻译： 3D多晶硅ROM及其制造方法
公开(公告)号：US06952038B2
公开(公告)日：2005-10-04
申请号：US10728767
申请日：2003-12-08
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Hsiang-Lan Lung , Chao-I Wu
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Hsiang-Lan Lung , Chao-I Wu
IPC分类号： H01L21/336 , H01L27/06 , H01L31/113
CPC分类号： H01L27/0688
摘要： A 3D polysilicon ROM including an isolated SiO2 layer on a silicon substrate, and an N+ polysilicon layer on the isolated SiO2 layer. The N+ polysilicon layer is further defined by a plurality of parallel, separate word lines. A first oxide layer fills the space between the word lines. A dielectric layer is deposited on the word lines and the first oxide layer. A P− polysilicon layer is deposited on the dielectric layer and further defines a plurality of parallel, separate bit lines. The bit lines overlap the word lines, from a top view, to form an approximately cross shape. The neck structure may be individually formed between the P− and N+ polysilicon layers by wet etching the dielectric layer with dilute hydrofluoric acid. A second oxide layer fills the space between the bit lines and is on the word lines and the first oxide layer.
摘要翻译：在硅衬底上包括隔离的SiO 2层的三维多晶硅ROM和分离的SiO 2层上的N +多晶硅层。 N +多晶硅层进一步由多个平行的单独的字线限定。第一氧化物层填充字线之间的空间。介电层沉积在字线和第一氧化物层上。 P-多晶硅层沉积在电介质层上并进一步限定多个平行的分开的位线。位线从顶视图与字线重叠，以形成大致十字形状。通过用稀氢氟酸湿式蚀刻介电层，可以在P和N +多晶硅层之间分别形成颈部结构。第二氧化物层填充位线之间的空间，并且位于字线和第一氧化物层上。

3. 发明申请

US20060104105A1 METHOD OF DETERMINING OPTIMAL VOLTAGES FOR OPERATING TWO-SIDE NON-VOLATILE MEMORY AND THE OPERATING METHODS 有权
标题翻译：确定用于操作两侧非易失性存储器的最佳电压的方法和操作方法
公开(公告)号：US20060104105A1
公开(公告)日：2006-05-18
申请号：US10991537
申请日：2004-11-17
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung
IPC分类号： G11C17/00
CPC分类号： G11C16/12 , G11C16/0475 , G11C16/26
摘要： A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I1-Vg curve of the first side and an I2-Vg curve of the second side are measured, wherein Vg is the gate voltage. A Gm1-Vg curve and a Gm2-Vg curve are plotted, wherein Gm1=dI1/dVg and Gm2=dI2/dVg. The optimal reading voltage VgO is determined as the gate voltage at the intersection of Gm1 and Gm2, corresponding to a maximal total current window Wm(=I2(VgO)−I1(VgO)).
摘要翻译：描述了一种确定用于读取用阈值电压Vt编程的双侧非易失性存储器的最佳读取电压的方法。存储器单元的第一侧被编程为Vt，然后第二侧的I 1 -T 1 -V G曲线和第二侧的I 2 -V -V曲线是测量，其中Vg是栅极电压。绘制了一个Gm 1-ΔVg曲线和一个Gm 2 -V -G曲线，其中G m 1 = 1/1 / / dVg和Gm2 = dI2 / dVg。确定最佳读取电压V g O O N作为在最大总电流窗口Gm1和Gm2的交点处的栅极电压 Wm（= I 2）（V g O O） - I 1（V g O O））。

4. 发明授权

US07038928B1 Method of determining optimal voltages for operating two-side non-volatile memory and the operating methods 有权
标题翻译：确定操作双侧非易失性存储器的最佳电压的方法和操作方法
公开(公告)号：US07038928B1
公开(公告)日：2006-05-02
申请号：US10991537
申请日：2004-11-17
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung
IPC分类号： G11C17/00
CPC分类号： G11C16/12 , G11C16/0475 , G11C16/26
摘要： A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I1-Vg curve of the first side and an I2-Vg curve of the second side are measured, wherein Vg is the gate voltage. A Gm1-Vg curve and a Gm2-Vg curve are plotted, wherein Gm1=dI1/dVg and Gm2=dI2/dVg. The optimal reading voltage VgO is determined as the gate voltage at the intersection of Gm1 and Gm2, corresponding to a maximal total current window Wm (=I2(VgO)−I1(VgO)).
摘要翻译：描述了一种确定用于读取用阈值电压Vt编程的双侧非易失性存储器的最佳读取电压的方法。存储器单元的第一侧被编程为Vt，然后第二侧的I 1 -T 1 -V G曲线和第二侧的I 2 -V -V曲线是测量，其中Vg是栅极电压。绘制了一个Gm 1-ΔVg曲线和一个Gm 2 -V -G曲线，其中G m 1 = 1/1 / / dVg和Gm2 = dI2 / dVg。确定最佳读取电压V g O O N作为在最大总电流窗口Gm1和Gm2的交点处的栅极电压 Wm（= I 2）（V g O O） - I 1（V g O O））。

5. 发明申请

US20100290293A1 METHOD OF IDENTIFYING LOGICAL INFORMATION IN A PROGRAMMING AND ERASING CELL BY ON-SIDE READING SCHEME 审中-公开
标题翻译：通过边界读取方案识别编程和擦除单元中的逻辑信息的方法
公开(公告)号：US20100290293A1
公开(公告)日：2010-11-18
申请号：US12845064
申请日：2010-07-28
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.
摘要翻译：公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

6. 发明授权

US07495967B2 Method of identifying logical information in a programming and erasing cell by on-side reading scheme 有权
标题翻译：通过旁路读取方案识别编程和擦除单元中的逻辑信息的方法
公开(公告)号：US07495967B2
公开(公告)日：2009-02-24
申请号：US11601710
申请日：2006-11-20
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.
摘要翻译：公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

7. 发明授权

US07209390B2 Operation scheme for spectrum shift in charge trapping non-volatile memory 有权
标题翻译：电荷捕获非易失性存储器频谱移位操作方案
公开(公告)号：US07209390B2
公开(公告)日：2007-04-24
申请号：US10876378
申请日：2004-06-24
申请人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh , Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
发明人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh , Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
IPC分类号： G11C16/00
CPC分类号： G11C16/3481 , G11C16/0466 , G11C16/3436
摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles. The charge retention properties can be greatly improved by these refill cycles.
摘要翻译：具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。通过这些再填充循环可以大大提高电荷保持性。

8. 发明授权

US07139200B2 Method of identifying logical information in a programming and erasing cell by on-side reading scheme 有权
公开(公告)号：US07139200B2
公开(公告)日：2006-11-21
申请号：US10873623
申请日：2004-06-23
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

9. 发明申请

US20060146613A1 PROGRAMMING METHOD FOR CONTROLLING MEMORY THRESHOLD VOLTAGE DISTRIBUTION 有权
标题翻译：用于控制存储器阈值电压分配的编程方法
公开(公告)号：US20060146613A1
公开(公告)日：2006-07-06
申请号：US11026799
申请日：2004-12-30
申请人： Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
发明人： Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
IPC分类号： G11C16/04
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/12 , G11C16/3459 , G11C16/3481
摘要： A method for programming one or more memory cells is disclosed. The one or more memory cells need to be two sides operated. After verifying both sides of each memory cell to identify the sides of the memory cells to be programmed, a programming voltage pulse is given to the first sides of the memory cells identified to be programmed. Another verification process is performed for both sides of each memory cell to identify the sides of the memory cells to be programmed. Next, a programming voltage pulse is given to the second sides of the memory cells identified to be programmed. The verifying both sides, programming the first sides, verifying both sides, and programming the second sides will continue until the both sides of each memory cell are programmed to a target programming voltage. The target programming voltage might have multiple voltage levels.
摘要翻译：公开了一种用于编程一个或多个存储器单元的方法。一个或多个存储单元需要是双面操作的。在验证每个存储器单元的两侧以识别待编程的存储器单元的侧面之后，将编程电压脉冲提供给被识别为被编程的存储器单元的第一侧。对每个存储单元的两侧执行另一个验证过程，以识别待编程的存储器单元的侧面。接下来，将编程电压脉冲提供给被识别为被编程的存储器单元的第二侧。验证两侧，编程第一面，验证双面，并对第二面进行编程将一直持续到每个存储单元的两侧都编程为目标编程电压。目标编程电压可能有多个电压电平。

10. 发明申请

US20050237816A1 Operation scheme for spectrum shift in charge trapping non-volatile memory 有权
标题翻译：电荷捕获非易失性存储器频谱移位操作方案
公开(公告)号：US20050237816A1
公开(公告)日：2005-10-27
申请号：US10876378
申请日：2004-06-24
申请人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh , Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
发明人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh , Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
IPC分类号： G11C11/36 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3481 , G11C16/0466 , G11C16/3436
摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles.
摘要翻译：具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。

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