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1. 发明授权

US06314472B1 Abort of DRAM read ahead when PCI read multiple has ended 失效
标题翻译：当PCI读取多个已经结束时，DRAM的中止被读取
公开(公告)号：US06314472B1
公开(公告)日：2001-11-06
申请号：US09203127
申请日：1998-12-01
申请人： Tuong P. Trieu , David D. Lent , Ashish S. Gadagkar , Vincent E. VonBokern , Zohar Bogin
发明人： Tuong P. Trieu , David D. Lent , Ashish S. Gadagkar , Vincent E. VonBokern , Zohar Bogin
IPC分类号： G06F300
CPC分类号： G06F13/161
摘要： A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.
摘要翻译：提供计算机系统。计算机系统包括主机处理器（HP），系统存储器（SM）以及输入/输出（I / O）主设备，以执行对SM的连续数据流的读取。计算机系统还包括耦合到HP，SM和I / O主设备的桥。当I / O主设备从SM读取连续的数据流时，桥接器向前读取SM。响应于I / O主设备的脱离接口，桥接器在对SM进行访问提交之前中止对SM的预读访问。

2. 发明授权

US06629217B1 Method and apparatus for improving read latency for processor to system memory read transactions 有权
标题翻译：用于提高处理器到系统存储器读取事务的读取延迟的方法和装置
公开(公告)号：US06629217B1
公开(公告)日：2003-09-30
申请号：US09469653
申请日：1999-12-22
申请人： Steve J. Clohset , Tuong P. Trieu , Wishwesh Gandhi
发明人： Steve J. Clohset , Tuong P. Trieu , Wishwesh Gandhi
IPC分类号： G06F1216
CPC分类号： G06F13/161
摘要： A method and apparatus for improving read latency for processor to system memory read transactions is disclosed. One embodiment of a system logic device includes logic that assumes a transfer size of a predetermined length. In this manner, the system logic device can issue a read transaction request to system memory as soon as the read request address is delivered by the processor rather than waiting for the processor to deliver information indicating the transfer length. Once the actual transfer length information is delivered from the processor to the system logic device, the system logic device determines whether any of the data returned by the system memory needs to be purged before returning the requested data to the processor.
摘要翻译：公开了一种用于改善处理器到系统存储器读取事务的读延迟的方法和装置。系统逻辑设备的一个实施例包括假定具有预定长度的传送大小的逻辑。以这种方式，一旦读请求地址由处理器传送，系统逻辑设备就可以向系统存储器发出读取事务请求，而不是等待处理器传递指示传送长度的信息。一旦将实际的传输长度信息从处理器传送到系统逻辑设备，则系统逻辑设备确定在将所请求的数据返回给处理器之前需要清除由系统存储器返回的任何数据。

3. 发明授权

US06330646B1 Arbitration mechanism for a computer system having a unified memory architecture 有权
标题翻译：具有统一存储架构的计算机系统的仲裁机制
公开(公告)号：US06330646B1
公开(公告)日：2001-12-11
申请号：US09226965
申请日：1999-01-08
申请人： Steve J. Clohset , Trung A. Diep , Wishwesh A. Gandhi , Thomas A. Piazza , Aditya Sreenivas , Tuong P. Trieu
发明人： Steve J. Clohset , Trung A. Diep , Wishwesh A. Gandhi , Thomas A. Piazza , Aditya Sreenivas , Tuong P. Trieu
IPC分类号： G06F1300
CPC分类号： G06F13/18
摘要： According to one embodiment, a computer system is disclosed that includes a memory and a memory controller coupled to the memory. The memory controller includes an arbitration unit that may be programmed to operate according to a first arbitration mode or a second arbitration mode. The computer system also includes a first device and a second device coupled to the arbitration unit. According to a further embodiment, the first device is assigned a higher priority classification than the second device for accessing the memory while the arbitration unit is operating according to the first arbitration mode. In addition, the first device and the second device are assigned equal priority classifications for accessing the memory while the arbitration unit is operating according to the second arbitration mode.
摘要翻译：根据一个实施例，公开了一种包括存储器和耦合到存储器的存储器控制器的计算机系统。存储器控制器包括可被编程为根据第一仲裁模式或第二仲裁模式进行操作的仲裁单元。计算机系统还包括耦合到仲裁单元的第一设备和第二设备。根据另一实施例，当仲裁单元根据第一仲裁模式操作时，第一设备被分配比用于访问存储器的第二设备更高的优先级分类。此外，当仲裁单元根据第二仲裁模式操作时，第一设备和第二设备被分配用于访问存储器的相同的优先级分类。

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