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1. 发明授权

US07319074B2 Method of defining polysilicon patterns 有权
标题翻译：定义多晶硅图案的方法
公开(公告)号：US07319074B2
公开(公告)日：2008-01-15
申请号：US11160178
申请日：2005-06-13
申请人： Pei-Yu Chou , Tong-Yu Chen
发明人： Pei-Yu Chou , Tong-Yu Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/31138 , H01L21/32137
摘要： The present invention provides a method of defining polysilicon patterns. The method forms a polysilicon layer on a substrate, and a patterned mask on the polysilicon layer. Then, a first etching process is performed to remove a portion of the polysilicon layer not covered by the mask, thus forming a plurality of cavities in the polysilicon layer. A strip process is performed to strip the mask utilizing gases excluding O2. Finally, a second etching process is performed to remove a portion of the polysilicon layer, thus extending the plurality of cavities down to a surface of the substrate.
摘要翻译：本发明提供了一种限定多晶硅图案的方法。该方法在衬底上形成多晶硅层，并在多晶硅层上形成图案化掩模。然后，进行第一蚀刻处理以去除未被掩模覆盖的多晶硅层的一部分，从而在多晶硅层中形成多个空腔。执行条带处理以利用除O 2以外的气体剥离掩模。最后，执行第二蚀刻工艺以去除多晶硅层的一部分，从而将多个空腔向下延伸到衬底的表面。

2. 发明申请

US20060281325A1 METHOD OF DEFINING POLYSILICON PATTERNS 有权
标题翻译：定义多晶硅图案的方法
公开(公告)号：US20060281325A1
公开(公告)日：2006-12-14
申请号：US11160178
申请日：2005-06-13
申请人： Pei-Yu Chou , Tong-Yu Chen
发明人： Pei-Yu Chou , Tong-Yu Chen
IPC分类号： H01L21/20
CPC分类号： H01L21/32139 , H01L21/31138 , H01L21/32137
摘要： The present invention provides a method of defining polysilicon patterns. The method forms a polysilicon layer on a substrate, and a patterned mask on the polysilicon layer. Then, a first etching process is performed to remove a portion of the polysilicon layer not covered by the mask, thus forming a plurality of cavities in the polysilicon layer. A strip process is performed to strip the mask utilizing gases excluding O2. Finally, a second etching process is performed to remove a portion of the polysilicon layer, thus extending the plurality of cavities down to a surface of the substrate.
摘要翻译：本发明提供了一种限定多晶硅图案的方法。该方法在衬底上形成多晶硅层，并在多晶硅层上形成图案化掩模。然后，进行第一蚀刻处理以去除未被掩模覆盖的多晶硅层的一部分，从而在多晶硅层中形成多个空腔。执行条带处理以利用除O 2以外的气体剥离掩模。最后，执行第二蚀刻工艺以去除多晶硅层的一部分，从而将多个空腔向下延伸到衬底的表面。

3. 发明授权

US08236702B2 Method of fabricating openings and contact holes 有权
标题翻译：制造开口和接触孔的方法
公开(公告)号：US08236702B2
公开(公告)日：2012-08-07
申请号：US12042340
申请日：2008-03-05
申请人： Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin , Po-Chao Tsao
发明人： Feng-Yi Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin , Po-Chao Tsao
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/76831 , H01L21/76897
摘要： A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.
摘要翻译：提供具有蚀刻停止层和至少从底部到顶部设置的电介质层的半导体衬底。然后对电介质层和蚀刻停止层进行图案化以形成暴露半导体衬底的多个开口。随后形成介电薄膜以覆盖电介质层，开口的侧壁和半导体衬底。然后去除设置在电介质层和半导体衬底上的电介质薄膜，同时保留设置在侧壁上的电介质薄膜。

4. 发明申请

US20120184105A1 METHOD OF FORMING OPENINGS 有权
标题翻译：形成开口的方法
公开(公告)号：US20120184105A1
公开(公告)日：2012-07-19
申请号：US13431945
申请日：2012-03-27
申请人： Pei-Yu Chou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Jiunn-Hsiung Liao
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338
摘要： A method for forming openings is provided. First, a substrate with a silicon-containing photo resist layer thereon is provided. Second, a first photo resist pattern is formed on the silicon-containing photo resist layer. Later, a first etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of first openings by using the first photo resist pattern as an etching mask. Next, a second photo resist pattern is formed on the silicon-containing photo resist layer. Then, a second etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of second openings by using the second photo resist pattern as an etching mask.
摘要翻译：提供一种形成开口的方法。首先，提供其上具有含硅光刻胶层的基板。其次，在含硅光致抗蚀剂层上形成第一光刻胶图案。然后，通过使用第一光致抗蚀剂图案作为蚀刻掩模，在含硅光致抗蚀剂层上进行第一蚀刻步骤以形成多个第一开口。接下来，在含硅光致抗蚀剂层上形成第二光致抗蚀剂图案。然后，通过使用第二光致抗蚀剂图案作为蚀刻掩模，在含硅光致抗蚀剂层上进行第二蚀刻步骤以形成多个第二开口。

5. 发明申请

US20110223768A1 Method for Forming Contact Opening 审中-公开
标题翻译：形成接触开口的方法
公开(公告)号：US20110223768A1
公开(公告)日：2011-09-15
申请号：US12720671
申请日：2010-03-10
申请人： Ying-Chih LIN , Pei-Yu Chou , Jiunn-Hsiung Liao , Feng-Yi Chang , Chih-Wen Feng , Shang-Yuan Tsai
发明人： Ying-Chih LIN , Pei-Yu Chou , Jiunn-Hsiung Liao , Feng-Yi Chang , Chih-Wen Feng , Shang-Yuan Tsai
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L21/02063 , H01L21/76802 , H01L21/76814
摘要： A method for forming contact openings is provided. First, a semiconductor device is formed on a substrate. Next, an etching stop layer, a first dielectric layer and a patterned photoresist layer are sequentially formed on the substrate. Next a portion of the first dielectric layer and a portion of the etching stop layer are removed to form an opening, wherein the portion of the first dielectric layer and the portion of the etching stop layer are not covered by the patterned photoresist layer. Next, the patterned photoresist layer is removed. Next, an over etching process is performed to remove the etching stop layer at a bottom of the opening and expose the semiconductor device in a nitrogen-free environment. The reactant gas of the over etching process includes fluorine-containing hydrocarbons, hydrogen gas and argon gas.
摘要翻译：提供了形成接触开口的方法。首先，在基板上形成半导体装置。接下来，在衬底上依次形成蚀刻停止层，第一电介质层和图案化光致抗蚀剂层。接下来，去除第一电介质层的一部分和蚀刻停止层的一部分以形成开口，其中第一介电层的一部分和蚀刻停止层的部分不被图案化的光致抗蚀剂层覆盖。接下来，去除图案化的光致抗蚀剂层。接下来，进行过蚀刻处理以去除开口底部的蚀刻停止层，并在无氮环境中暴露半导体器件。过蚀刻工艺的反应气体包括含氟烃，氢气和氩气。

6. 发明申请

US20110076814A1 METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTOR 有权
标题翻译：制备应变硅CMOS晶体管的方法
公开(公告)号：US20110076814A1
公开(公告)日：2011-03-31
申请号：US12959393
申请日：2010-12-03
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.
摘要翻译：首先，提供具有第一有源区和第二有源区的半导体基板。第一有源区包括第一晶体管，第二有源区包括第二晶体管。第一蚀刻停止层，应力层和第二蚀刻停止层设置在第一晶体管，第二晶体管和隔离结构上。通过使用设置在第一有源区上的图案化光致抗蚀剂作为掩模来执行第一蚀刻工艺，以从第二有源区移除第二蚀刻停止层和应力层的一部分。去除图案化的光致抗蚀剂，并且通过使用第一有源区的第二蚀刻停止层作为掩模来执行第二蚀刻工艺，以从第二有源区去除剩余的应力层和第一蚀刻停止层的一部分。

7. 发明申请

US20110068408A1 STRAINED-SILICON CMOS TRANSISTOR 审中-公开
标题翻译：应变硅CMOS晶体管
公开(公告)号：US20110068408A1
公开(公告)日：2011-03-24
申请号：US12959399
申请日：2010-12-03
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strained-silicon CMOS transistor includes: a semiconductor substrate having a first active region, a second active region, and an isolation structure disposed between the first active region and the second active region; a first transistor, disposed on the first active region; a second transistor, disposed on the second active region; a first etching stop layer, disposed on the first transistor and the second transistor; a first stress layer, disposed on the first transistor; a second etching stop layer, disposed on the first transistor and the first stress layer, wherein an edge of the first stress layer is aligned with that of the second etching stop layer; a second stress layer, disposed on the second transistor; and a third etching stop layer disposed on the second transistor and the second stress layer, wherein an edge of the second stress layer is aligned with that of the third etching stop layer.
摘要翻译：应变硅CMOS晶体管包括：具有第一有源区，第二有源区和设置在第一有源区和第二有源区之间的隔离结构的半导体衬底; 第一晶体管，设置在第一有源区上; 第二晶体管，设置在第二有源区上; 第一蚀刻停止层，设置在第一晶体管和第二晶体管上; 第一应力层，设置在所述第一晶体管上; 第二蚀刻停止层，设置在第一晶体管和第一应力层上，其中第一应力层的边缘与第二蚀刻停止层的边缘对准; 第二应力层，设置在所述第二晶体管上; 以及设置在所述第二晶体管和所述第二应力层上的第三蚀刻停止层，其中所述第二应力层的边缘与所述第三蚀刻停止层的边缘对准。

8. 发明申请

US20090145877A1 METHOD FOR CONTROLLING ADI-AEI CD DIFFERENCE RATIO OF OPENINGS HAVING DIFFERENT SIZES 有权
标题翻译：用于控制具有不同尺寸的开口的ADI-AEI CD差异比例的方法
公开(公告)号：US20090145877A1
公开(公告)日：2009-06-11
申请号：US12371809
申请日：2009-02-16
申请人： Feng-Yih Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
发明人： Feng-Yih Chang , Pei-Yu Chou , Jiunn-Hsiung Liao , Chih-Wen Feng , Ying-Chih Lin
IPC分类号： B44C1/22
CPC分类号： H01L21/76804 , H01L21/31144 , H01L21/76895
摘要： A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.
摘要翻译：描述了用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法。开口依次形成为含硅材料层，蚀刻电阻层和靶材料层。在开口蚀刻步骤之前，光致抗蚀剂掩模中的至少一个开口图案的尺寸通过基本上保形的聚合物层的光致抗蚀剂修饰或沉积而改变。执行在更宽的开口图案的侧壁上形成较厚聚合物的第一蚀刻步骤以形成图案化的含Si材料层。执行第二蚀刻步骤以去除蚀刻电阻层和目标材料层的暴露部分。控制光致抗蚀剂修整或聚合物层沉积步骤的参数中的至少一个参数和第一蚀刻步骤的蚀刻参数以获得预定的ADI-AEI CD差异比。

9. 发明授权

US07524742B2 Structure of metal interconnect and fabrication method thereof 有权
标题翻译：金属互连结构及其制造方法
公开(公告)号：US07524742B2
公开(公告)日：2009-04-28
申请号：US11748472
申请日：2007-05-14
申请人： Pei-Yu Chou , Chun-Jen Huang
发明人： Pei-Yu Chou , Chun-Jen Huang
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/76844 , H01L21/76802 , H01L21/76814 , H01L21/76829
摘要： A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.
摘要翻译：金属互连的工艺和结构包括：使用第一图案化硬掩模提供具有第一电导体的基板，形成第一介电层和第一图案化硬掩模，以形成第一开口和第二导电体，形成第二导体电介质层和第二图案化硬掩模，使用第二图案化硬掩模作为蚀刻掩模，并使用第一图案化硬掩模作为蚀刻停止层以形成第二开口和第三导电体。

10. 发明授权

US07517766B2 Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device 有权
标题翻译：去除间隔物的方法，制造金属氧化物半导体晶体管器件的方法和金属氧化物半导体晶体管器件
公开(公告)号：US07517766B2
公开(公告)日：2009-04-14
申请号：US11531260
申请日：2006-09-12
申请人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
发明人： Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6653 , H01L29/7833 , H01L29/7843
摘要： A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.
摘要翻译：一种去除间隔物的方法，制造金属氧化物半导体晶体管器件的方法和金属氧化物半导体晶体管器件，其中在去除间隔物之前，保护层沉积在间隔物上形成在源极/漏极区域上的材料层（例如自对准硅化物层）和栅电极，使得隔离物上的保护层的厚度小于材料层上的厚度，然后保护层部分去除，使得隔离物上的保护层的厚度近似为零，并且保护层的一部分保留在材料层上。因此，当去除间隔物时，材料层可被保护层保护。

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