专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2009099613A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009099613A
公开(公告)日：2009-05-07
申请号：JP2007267047
申请日：2007-10-12
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , Univ Of Tokushima , トヨタ自動車株式会社 , 国立大学法人徳島大学 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , UEDA HIROYUKI , UESUGI TSUTOMU , KACHI TORU , ONO YASUO , GO KINPEI , HU CHENGYU
IPC分类号： H01L21/28 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To form an ohmic electrode by repairing damage by etching.
SOLUTION: A method of manufacturing a semiconductor device comprises: a surface layer forming step of forming a heterogeneous surface layer on a surface of a p-type nitride semiconductor; an etching step of exposing the surface of the p-type nitride semiconductor by removing part of the surface layer; an annealing step of subjecting the p-type nitride semiconductor after the etching step to a heating process; and an electrode forming step of forming electrodes on the surface of the p-type nitride semiconductor after the annealing step. The annealing step is characterized by being executed in a nitrogen or oxygen atmosphere at 700-1,200°C.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过蚀刻修复损伤来形成欧姆电极。解决方案：制造半导体器件的方法包括：在p型氮化物半导体的表面上形成非均匀表面层的表面层形成步骤; 蚀刻步骤，通过去除表面层的一部分来暴露p型氮化物半导体的表面; 在蚀刻步骤之后对p型氮化物半导体进行加热处理的退火步骤; 以及在退火步骤之后在p型氮化物半导体的表面上形成电极的电极形成步骤。退火步骤的特征在于在氮气或氧气氛中在700-1200℃下进行。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009038070A Nitride semiconductor device and manufacturing method thereof 审中-公开
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：JP2009038070A
公开(公告)日：2009-02-19
申请号：JP2007198552
申请日：2007-07-31
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , Univ Of Tokushima , トヨタ自動車株式会社 , 国立大学法人徳島大学 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , UEDA HIROYUKI , UESUGI TSUTOMU , KACHI TORU , ONO YASUO , GO KINPEI , HU CHENGYU
IPC分类号： H01L21/28 , H01L33/32 , H01L33/40 , H01L33/44 , H01S5/042
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a nitride semiconductor device comprising a p-type nitride semiconductor layer, an insulating film covering the nitride semiconductor layer and formed with a through hole, and a metal film in contact with the nitride semiconductor layer exposed at the bottom face of the through hole, which method being able to actualize good ohmic characteristics.
SOLUTION: A silicon oxide film 4 is formed on the surface of a p-type gallium nitride layer 2. Then, part of the silicon oxide film 4 is etched, and a through hole 6 reaching the surface of the gallium nitride layer 2 is formed. Then, silicon 8 adhered to the surface of the gallium nitride layer 2 is removed. Then, a metal film in contact with the surface of the gallium nitride layer 2 is formed. Then, the gallium nitride layer 2, the silicon oxide film 4, and the metal film are heat-treated. The process for removing the silicon 8 and the process for forming the metal film are carried out under atmosphere containing no silicon.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种氮化物半导体器件的制造方法，该氮化物半导体器件包括p型氮化物半导体层，覆盖氮化物半导体层并形成有通孔的绝缘膜，以及与氮化物半导体层暴露在通孔的底面，该方法能够实现良好的欧姆特性。解决方案：在p型氮化镓层2的表面上形成氧化硅膜4.然后，蚀刻氧化硅膜4的一部分，并且到达氮化镓层表面的通孔6 形成2。然后，去除附着在氮化镓层2的表面上的硅8。然后，形成与氮化镓层2的表面接触的金属膜。然后，对氮化镓层2，氧化硅膜4和金属膜进行热处理。去除硅8的工艺和形成金属膜的工艺在不含硅的气氛下进行。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2014157896A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014157896A
公开(公告)日：2014-08-28
申请号：JP2013027352
申请日：2013-02-15
申请人： Toyota Central R&D Labs Inc , 株式会社豊田中央研究所 , Toyota Motor Corp , トヨタ自動車株式会社 , Denso Corp , 株式会社デンソー
发明人： WATANABE YUKIHIKO , AOI SACHIKO , SUGIMOTO MASAHIRO , SOENO AKITAKA , MIYAHARA SHINICHIRO
IPC分类号： H01L29/78 , H01L21/329 , H01L21/336 , H01L27/04 , H01L29/12 , H01L29/47 , H01L29/872
CPC分类号： H01L29/47 , H01L21/0485 , H01L21/28518 , H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/78 , H01L29/7806 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same which use a silicon carbide with a built-in Schottky barrier diode capable of being manufactured in a simplified manufacturing process as a semiconductor material.SOLUTION: A manufacturing method of a semiconductor device 1 comprises: a process of forming ohmic electrodes 14 within first ranges 1A on one principal surface of a silicon carbide layer 20; a process of siliciding the ohmic electrodes 14; and a process of forming a Schottky electrode 16 in a self-alignment manner within a second range 2A on the one principal surface of the silicon carbide layer 20, which is exposed between the ohmic electrodes 14.
摘要翻译：要解决的问题：提供一种半导体器件及其制造方法，该半导体器件及其制造方法使用具有能够以简化的制造工艺制造的内置肖特基势垒二极管作为半导体材料的碳化硅。解决方案：半导体器件1包括：在碳化硅层20的一个主表面上的第一范围1A内形成欧姆电极14的工艺; 将欧姆电极14硅化的工艺; 以及在二氧化硅层20的暴露在欧姆电极14之间的一个主表面上的第二范围2A内以自对准方式形成肖特基电极16的工艺。

4. 发明专利

JP2012178403A Semiconductor device including p-type group-iii nitride semiconductor layer 有权
标题翻译：包含P型III族氮化物半导体层的半导体器件
公开(公告)号：JP2012178403A
公开(公告)日：2012-09-13
申请号：JP2011039671
申请日：2011-02-25
申请人： Toyota Motor Corp , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , KANECHIKA MASAKAZU , UESUGI TSUTOMU , KIKUTA DAIGO , NARITA TETSUO , IGUCHI HIROKO
IPC分类号： H01L29/812 , H01L21/336 , H01L21/337 , H01L21/338 , H01L29/12 , H01L29/778 , H01L29/78 , H01L29/808
摘要： PROBLEM TO BE SOLVED: To solve the problem that, in the case where a through-hole is formed in a p-type group-III nitride semiconductor layer and the through-hole is filled with an n-type group-III nitride semiconductor, an impurity concentration of the n-type group-III nitride semiconductor with which the through-hole is filled becomes high, so that a current easily flows on a junction interface of the p-type group-III nitride semiconductor and the n-type group-III nitride semiconductor and voltage resistance is reduced easily.SOLUTION: The distribution of impurity concentrations is provided in a p-type group-III nitride semiconductor layer 8. Within a range 8b facing a through-hole 8c, the impurity concentration is made low and within a range 8a away from the through-hole 8c, the impurity concentration is made high. While a semiconductor device is off, a depletion layer is spread wide in the range 8b of low impurity concentration, and required voltage resistance can be secured.
摘要翻译：解决的问题为了解决在p型III族氮化物半导体层中形成贯通孔的情况下，在通孔中填充有n型III族氮化物半导体，填充有通孔的n型III族氮化物半导体的杂质浓度变高，使得电流容易在p型III族氮化物半导体的接合界面上流动，n型型III族氮化物半导体和耐压性容易降低。
解决方案：在p型III族氮化物半导体层8中提供杂质浓度的分布。在面向通孔8c的范围8b内，杂质浓度低，并且在距离通孔8c，杂质浓度变高。当半导体器件关闭时，耗尽层在低杂质浓度的范围8b内扩展宽，并且可以确保所需的耐电压。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2010219384A Semiconductor device comprised of group iii nitride semiconductor, and manufacturing method thereof 有权
标题翻译：由III族氮化物半导体组成的半导体器件及其制造方法
公开(公告)号：JP2010219384A
公开(公告)日：2010-09-30
申请号：JP2009065838
申请日：2009-03-18
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： NARITA TETSUO , ITO KENJI , KIGAMI MASAHITO , SUGIMOTO MASAHIRO
IPC分类号： H01L21/28 , H01L21/338 , H01L29/417 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device structured to take ohmic contact even with a low-concentration n-type group III nitride semiconductor. SOLUTION: In a sample 1, a non-doped GaN layer 11 and an Si-doped n-GaN layer 12 are formed on a sapphire substrate 10 and on the n-GaN layer 12, two electrodes 14a, 14b comprised of Ti/Al are separately formed via an AlN film 13. The electrode 14a, 14b is a non-alloyed electrode on which alloying using thermal treatment has not been performed. At a side of the n-GaN layer 12 on an interface of the AlN film 13 and the n-GaN layer 12, a two-dimensional (2D) electron gas layer 15 is formed. Through the 2D electron gas layer 15, the electrodes 14a, 14b can be brought into contact with the n-GaN layer 12 with low resistance. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供构造成即使使用低浓度n型III族氮化物半导体也可以接触欧姆接触的半导体器件。解决方案：在样品1中，在蓝宝石衬底10上和n-GaN层12上形成非掺杂GaN层11和掺杂Si的n-GaN层12，由n-GaN层12组成的两个电极14a，14b Ti / Al通过AlN膜13分别形成。电极14a，14b是未进行使用热处理的合金化的非合金电极。在AlN膜13和n-GaN层12的界面上的n-GaN层12的一侧形成二维（2D）电子气体层15。通过2D电子气体层15，电极14a，14b可以以低电阻与n-GaN层12接触。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2010050280A Nitride semiconductor device 审中-公开
标题翻译：氮化物半导体器件
公开(公告)号：JP2010050280A
公开(公告)日：2010-03-04
申请号：JP2008213193
申请日：2008-08-21
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , UEDA HIROYUKI , KANECHIKA MASAKAZU , UESUGI TSUTOMU , KACHI TORU
IPC分类号： H01L21/338 , H01L29/778 , H01L29/786 , H01L29/80 , H01L29/812
CPC分类号： H01L29/2003 , H01L21/28264 , H01L29/41766 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/7787 , H01L29/7788
摘要： PROBLEM TO BE SOLVED: To provide a nitride semiconductor device 2 which has normally-off characteristics.
SOLUTION: The nitride semiconductor device 2 has a nitride semiconductor layer 10, made of undoped AlGaN, laminated on a surface of a nitride semiconductor lower layer 8 made of undoped GaN. The nitride semiconductor layer 10 has a larger band gap than the nitride semiconductor lower layer 8, and forms a heterojunction with the nitride semiconductor lower layer 8. A gate insulating film 16 is formed on a surface of the nitride semiconductor layer 10. The gate insulating film 16 includes a portion formed of a nitride aluminum film 15 and a portion formed of an insulating substance 14 containing oxygen or silicon. A range W2 where the nitride aluminum film 15 is formed is included in a range W1 where a gate electrode 18 is formed.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有常关特性的氮化物半导体器件2。解决方案：氮化物半导体器件2具有层叠在由未掺杂的GaN制成的氮化物半导体下层8的表面上的由未掺杂的AlGaN制成的氮化物半导体层10。氮化物半导体层10具有比氮化物半导体下层8更大的带隙，并且与氮化物半导体下层8形成异质结。在氮化物半导体层10的表面上形成栅极绝缘膜16。膜16包括由氮化物铝膜15形成的部分和由含有氧或硅的绝缘物质14形成的部分。其中形成氮化物铝膜15的范围W2包括在形成栅电极18的范围W1中。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2010027639A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010027639A
公开(公告)日：2010-02-04
申请号：JP2008183496
申请日：2008-07-15
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UESUGI TSUTOMU , KANECHIKA MASAKAZU , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/338 , H01L29/423 , H01L29/47 , H01L29/49 , H01L29/80 , H01L29/812 , H01L29/872
CPC分类号： H01L29/8122 , H01L29/0623 , H01L29/0657 , H01L29/1029 , H01L29/1037 , H01L29/1075 , H01L29/1079 , H01L29/42316 , H01L29/7828 , H01L29/7832 , H01L29/7838 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a technology which decreases the on resistance while ensuring high breakdown voltage in a semiconductor device having a gate electrode provided between a pair of main electrodes.
SOLUTION: The semiconductor device 100 is provided with a gate electrode 10 between a pair of main electrodes 2 and 22. The gate portion 10 has an insulated gate electrode portion 10a and a Schottky electrode portion 10b. The semiconductor device 100 has a contact region 18 for connection with the main electrodes 2, a channel semiconductor region 8 which adjoins the contact region 18, a p-type semiconductor region 20 adjacent to the backside of the channel semiconductor region 8, and a drift semiconductor region 12 which adjoins both the channel semiconductor region 8 and the p-type semiconductor region 20. The insulated gate electrode portion 10a faces the surface of the contact region 18 with a gate insulating film 4 interposed therebetween. The Schottky electrode portion 10b is in direct contact with the surface of the drift semiconductor region 12.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种在具有设置在一对主电极之间的栅电极的半导体器件中确保高击穿电压的同时降低导通电阻的技术。解决方案：半导体器件100在一对主电极2和22之间设置有栅电极10.栅极部分10具有绝缘栅电极部分10a和肖特基电极部分10b。半导体器件100具有用于与主电极2连接的接触区域18，与接触区域18相邻的沟道半导体区域8，与沟道半导体区域8的背面相邻的p型半导体区域20，半导体区域12，其与沟道半导体区域8和p型半导体区域20相邻。绝缘栅电极部分10a在其间插入有栅极绝缘膜4，面对接触区域18的表面。肖特基电极部分10b与漂移半导体区域12的表面直接接触。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2009302388A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009302388A
公开(公告)日：2009-12-24
申请号：JP2008156824
申请日：2008-06-16
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： UEDA HIROYUKI , KANECHIKA MASAKAZU , UESUGI TSUTOMU , KACHI TORU , SUGIMOTO MASAHIRO
IPC分类号： H01L21/338 , H01L21/28 , H01L21/285 , H01L21/768 , H01L23/522 , H01L29/778 , H01L29/78 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To minimize a current leaking from an element region in a semiconductor device having a hetero-junction.
SOLUTION: A semiconductor device 100 has a semiconductor multilayer portion 11 where nitride semiconductor layers 6 and 10 having different band gaps are laminated, and the semiconductor multilayer portion 11 has an element region 100a and an element isolation region 100b formed around the element region 100a. The element region 100a is isolated from other regions by the element isolation region 100b. A step of manufacturing the semiconductor device 100 includes a step of forming a pair of electrode groups 24 and 16 which are connected with a main electrode on the surface of the semiconductor multilayer portion 11 in the element region 100a, and a step of forming a sputter layer 12 on the surface of the semiconductor multilayer portion 11 in the element isolation region 100b by using a sputtering method.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：使具有异质结的半导体器件中的元件区域的电流泄漏最小化。解决方案：半导体器件100具有层叠有不同带隙的氮化物半导体层6和10的半导体多层部分11，并且半导体多层部分11具有元件区域100a和形成在元件周围的元件隔离区域100b 区域100a。元件区域100a通过元件隔离区域100b与其它区域隔离。制造半导体器件100的步骤包括在元件区域100a中形成与半导体多层部分11的表面上的主电极连接的一对电极组24和16的步骤，以及形成溅射层12通过溅射法在元件隔离区域100b中的半导体多层部分11的表面上。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009212291A Semiconductor device, and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009212291A
公开(公告)日：2009-09-17
申请号：JP2008053543
申请日：2008-03-04
申请人： Hokkaido Univ , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 国立大学法人北海道大学 , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , SOEJIMA SHIGEMASA , UESUGI TSUTOMU , KACHI TORU , HASHIZUME TAMOTSU , SATO TAKETOMO
IPC分类号： H01L21/338 , H01L29/778 , H01L29/78 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof, reducing a reduction in drain current incidental to operating temperature rise in the semiconductor device having heterojunction of a nitride semiconductor layer.
SOLUTION: An HEMT 100 includes a semiconductor substrate 5 on which an undoped GaN layer 2 and an n-type AlGaN layer 4 are laminated in this order, a source electrode 6 and a drain electrode 10 formed on a surface of the semiconductor substrate 5 and a gate electrode 8 formed between the source electrode 6 and the drain electrode 10. A group of a plurality of recessed parts 14, each defining a first side face 12a extending in a direction of linking the source electrode 6 with the drain electrode 10 and a second side face 12b extending orthogonal to the first side face, is formed in the surface of the semiconductor substrate 5. The gate electrode 8 covers the first and second side faces 12a, 12b. In the HEMT 100, mesa-type conduction channels are connected in parallel.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体器件及其制造方法，减少了在具有氮化物半导体层的异质结的半导体器件中附带的工作温度升高的漏极电流的减少。解决方案：HEMT 100包括其上依次层叠未掺杂的GaN层2和n型AlGaN层4的半导体衬底5，形成在半导体的表面上的源电极6和漏电极10 基板5和形成在源极电极6和漏电极10之间的栅电极8.一组多个凹部14，每个凹部14限定在将源电极6与漏电极连接的方向上延伸的第一侧面12a 在半导体衬底5的表面上形成有与第一侧面正交的第二侧面12b和第二侧面12b。栅电极8覆盖第一和第二侧面12a，12b。在HEMT 100中，台面型导通通道并联连接。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2009094337A Method of manufacturing semiconductor element 审中-公开
标题翻译：制造半导体元件的方法
公开(公告)号：JP2009094337A
公开(公告)日：2009-04-30
申请号：JP2007264354
申请日：2007-10-10
申请人： Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SOEJIMA SHIGEMASA , SUGIMOTO MASAHIRO
IPC分类号： H01L21/20 , H01L21/338 , H01L29/778 , H01L29/80 , H01L29/812
CPC分类号： H01L29/7788 , H01L29/2003
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device composed of a p-type group III nitride semiconductor, the group III nitride semiconductor being not decreased in hole density.
SOLUTION: The manufacturing method of the semiconductor device composed of the group III nitride semiconductor includes a plurality of heat treatment processes of ≥400°C in temperature after formation of the group III nitride semiconductor layer doped with Mg. In heat treatment processes of ≥400°C in temperature other than the final process, heat treatments are carried out in an ammonia atmosphere and in the final heat treatment process of ≥400°C in temperature, a heat treatment is carried out in a nitrogen atmosphere. The heat treatments are thus performed to manufacture the semiconductor element without decreasing the hole density of the p-type group III nitride semiconductor layer.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：为了提供由p型III族氮化物半导体构成的半导体器件的制造方法，III族氮化物半导体的孔密度不降低。解决方案：由III族氮化物半导体构成的半导体器件的制造方法包括在形成掺杂有Mg的III族氮化物半导体层之后的温度为≥400℃的多个热处理工艺。在最终工艺以外的温度≥400℃的热处理工艺中，在氨气氛中进行热处理，在最终热处理过程中，在400℃以上的温度下，在氮气中进行热处理大气层。由此进行热处理以制造半导体元件而不降低p型III族氮化物半导体层的空穴密度。版权所有（C）2009，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式